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TMS320F28377(D) memory map

Tjarco Boerkoel
Expert 1725 points

Hi All,

The TMS320F28377(D) has Harvard architecture, which is nice, but I can't find the dual mapped memory and peripheral addresses in the datasheet. I only find the ?data-space-mapped? addresses. In the TMS320F2833x the dual mapped addresses have a 2nd memory address specified for program space (+0x3F0000).

If the program-space mapped registers have a offset (like +0x3F0000) am I able to use these addresses with the CLA? Because CLA i's using 16bit adressing?

Or does the linker handle this? Is it enough to set the "page" to zero or one in the command linker file for determining whether the data is fetched through data or program memory bus?

It's a bit confusing..

Best regards,

Tjarco

  • 0
    TI__Mastermind 20850 points

    Hi Tjarco

    Tjarco Boerkoel said:
    If the program-space mapped registers have a offset (like +0x3F0000) am I able to use these addresses with the CLA? Because CLA i's using 16bit adressing?

    I was looking through the datasheet and i dont think the 28377D RAM is dual mapped like the 2833x. I will double check this. In any case the CLA can only access the lower 64Kwords of RAM since it has a 16-bit program address bus.

    Tjarco Boerkoel said:
    Or does the linker handle this? Is it enough to set the "page" to zero or one in the command linker file for determining whether the data is fetched through data or program memory bus?

    We have a unified memory, meaning that the data and program buses are connected to the entire memory space, there isn't a physically separate data, program space -  the linker command file makes a logical distinction between the two spaces using PAGE 0 and 1 designations. Data is usually fetched using the data bus, there are a few asm instructions that will use the program bus to get data (restricted to the lower 4Mwords).