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lost SPI synchronization when higher priority interrupts are used

Lebing Jin
Intellectual 390 points

Other Parts Discussed in Thread: TMS320F28069

Hello,

I'm testing the communication between two DSPs (TMS320F28069) via SPI (interrupt mechanism).

When I implement simple code in both master and slave, everything works very well. By 'simple code', I mean only RX and TX interrupts are used.  

However, when I add interrupts EPWM1_INT and ADCINT1 to the program, the two DSPs lost sychconization (missing or mis-receiving data).  I'm thinking perhaps this is caused by the interrupt priority issue. RX and TX interrupt have lower priority. Does anyone know how to solve this issue? Or did I misunderstand anything?

The thing I want to do is transmitting the sampled data (obtained from ADC)  between two DSPs .

Thank you for your help.

  • 0
    TI__Guru* 84230 points

    Lebing,

    The ADC, with its speed and amount of data has the ability to occupy alot of time when the ADCISR comes in.  I would compare your sample rate and cycles in your ADC ISR to see how much and how often you expect to be in there.

    An alternative would be to nest/re-enalble other interrupts once in the ADC ISR if needed.

    http://processors.wiki.ti.com/index.php/Interrupt_Nesting_on_C28x

    Another alternative would be to pass ADC tasks to the CLA.  Independent of the main C28x the CLA can recognize ADC INTs and pull the data and store it somewhere or process then store it to be acted upon.

    Matt

  • 0 in reply to MatthewPate
    Intellectual 390 points

    Hi Matt,

    Thank you for your reply.

    I checked the link you suggested, it is said 'Do not modify PIEIER registers outside of an ISR for that group. For example, PIEIER1 should only be modified within an ISR from group 1. Likewise PIEIER2 should only be modified within a group 2 ISR.' In my case, ADC INT is in group 1 while SPI INT is in group 6. Does this mean I can't use this nest/re-enable mechanism?

    BR,

    Lebing