Hello community,
I have some problems with the current limitation by CBC TZ events. I'm developing a PFC stage and for safety reasons this current limitaion is necessary. For cost reduction reasons the internal comperators are used to trip these CBC events. For testing I set a reduced current limit by the internal DAC to 4A and increased the current until it reached that limit. When the current reaches the limit, it is not limited. Instead it results in very high current peaks.
My configuration looks like follows:
// Comparator 1 setup
// Comparator/DAC logic is powered up @ Enable DAC-Comparator
Comp1Regs.COMPCTL.bit.COMPDACEN = 1;
// 0 = Inverting input of comparator connected to internal DAC
Comp1Regs.COMPCTL.bit.COMPSOURCE = 0;
// Over current measured by 12bit ADC --> OVC at 14A
// DAC 1023 = 17A --> 841 = 14A
Comp1Regs.DACVAL.bit.DACVAL = 240; //4A
// Asynchronous version of comparator output is passed
Comp1Regs.COMPCTL.bit.SYNCSEL = 0;
// Qualification Period for synchronized output of the comparator
Comp1Regs.COMPCTL.bit.QUALSEL = 0;
// Non inverted output
// Active High Trip Zone event
Comp1Regs.COMPCTL.bit.CMPINV = 0;
//-----------------------------------------------------------------
// Current limiting TRIP-Zone Phase A
// DCxEVT1 events can be defined as one-shot events
// DCxEVT2 events can be defined as cycle-by-cycle
// Note: A events for EPWMxA and B events for EPWMxB
// If Comparator1A input exceeds limit (output becomes high), TZ event is invoked
// Define an event (DCAEVT2) for EPWM2A
EPwm2Regs.TZSEL.bit.DCAEVT2 = 1; // Defined as CBC
// Trip Action On EPWM2A --- If trip occurs (OVC) force EPWM2A to low (2 = force low)
EPwm2Regs.TZCTL.bit.DCAEVT2 = 2;
// Define digital compare output event selection
// DCAEVT2 = DCAH = high (will become active as COMPARATOR 1 output goes high) DCAL = Don't care
EPwm2Regs.TZDCSEL.bit.DCAEVT2 = 2;
// DCAH = input from COMPARATOR 1 output (8)
EPwm2Regs.DCTRIPSEL.bit.DCAHCOMPSEL = 8;
// DCAEVT2 not filtered
EPwm2Regs.DCACTL.bit.EVT2SRCSEL = 0;
// Take async path
EPwm2Regs.DCACTL.bit.EVT2FRCSYNCSEL = 1;
The EPWM is in up-down count mode and uses two compare events for PWM generation. I would be glad about some advice and if there are further information required, please just ask me.
Thank you in advance
D. Beinlich
