hi Folks,
Im looking at implementing slave I2C for SMBus on an F28027. One of the SMBus protocols is quick command which consists of just the address byte, where the intended information is just the R/W# bit of the address byte.
In this case will both the addressed as a slave and stop condition detected conditions will be true by the time the I2C interrupt vectors?
If so which value will be in the I2CISRC register INTCODE field?
If the interrupt vectors after the START but before the STOP then the I2CISRC.INTCODE will be 111b and the ISR may have to wait to see if the I2CSTR.SCD will be set.
If the interrupt vectors after the STOP then the I2CISRC.INTCODE will be 110b (?) and the I2CSTR.AAS and SDIR bit will have already been cleared making the protocol unfeasible (as it needs the SDIR bit).
Thanks