F28335 - CAN TXD pin output problem

Sneha Thakur

Expert 2660 points

Other Parts Discussed in Thread: ISO1050, CONTROLSUITE, ISO1050EVM

I am not able to get toggling output at TXD pin of CAN.The code is attached below for F28335.Kindly Help me out..

Is the program correct? Can someone please help out.

CAN-Rx

Fullscreen 5734.can-rx.txt Download

//
//      Lab CAN_2  : TMS320F2812
//      (C) Frank Bormann
//
//###########################################################################
//
// FILE:    Lab_CAN_2.c
//
// TITLE:   DSP28 CAN - Receive with the Zwickau-adapterboard
//
//          Extended CAN-Frame is received with 1 MBPS
//          from highspeed-CAN
//          Jumper JP4 :  2-3  ( 120 Ohm enabled)
//          Jumper JP5 :  1-2  ; Jumper JP6 _ 1-2 ( highspeed transceiver SN


//
//          Aim of the test :
//          Receive a 1 byte dataframe with Identifier 0x10000000
//          and show the databyte on the LED's at GPIO-Port B7...B0
//          Mailbox 1 is used as receiver
//          Identifier : 0x1000 0000
//          DLC =  1
//
//          Frequency Osscillator : 30MHz
//          PLLCR = 0xA   :  multiply by 5
//          SYSCLKOUT = CLKIN = 150MHz
//          Highspeed - Prescaler (HISPCP = 0x0001; div by 2 ) : 75 Mhz
//          Lowspeed - Prescaler (LOSPCP  = 0x0002; div by 4 ) : 37.5 Mhz
//###########################################################################
//
//  Ver | dd mmm yyyy | Who  | Description of changes
// =====|=============|======|===============================================
//  1.0 | 09 May 2003 | F.B. | Startup Version for Lab_CAN_2
//  2.0 | 27 Nov 2003 | F.B. | adapted to header-files Version 1.00
//###########################################################################

// CAUTION :  DSP281x_ECan.h  , Version 1.0 ( Hareesh) contains an error
// the byte field of struct  CANMDL_BYTES and CANMDH_BYTES
// have the wrong order ( Byte1 to 4)instead of Byte 4 to 1)
// MODIFY  :  inside DSP281x_ECan.h modify the two structures to :
// struct  CANMDL_BYTES {      // bits   description
//   Uint16      BYTE3:8;     // 31:24
//   Uint16      BYTE2:8;     // 23:16
//   Uint16      BYTE1:8;     // 15:8
//   Uint16      BYTE0:8;     // 7:0
// };
//
// struct  CANMDH_BYTES {      // bits   description
//   Uint16      BYTE7:8;     // 63:56
//   Uint16      BYTE6:8;     // 55:48
//   Uint16      BYTE5:8;     // 47:40
//   Uint16      BYTE4:8;     // 39:32
// };
//##########################################################################

#include "DSP28x_Project.h"

#define IDENTIFIER 0x10000000

// Prototype statements for functions found within this file.

void Gpio_select(void);

// Global Variables

/* Create a shadow register structure for the CAN control registers. This is
 needed, since, only 32-bit access is allowed to these registers. 16-bit access
 to these registers could potentially corrupt the register contents. This is
 especially true while writing to a bit (or group of bits) among bits 16 - 31 */

struct  ECAN_REGS ECanaShadow;

main()
{
// Initialize System Control registers, PLL, WatchDog, Clocks to default state:
// This function is found in the DSP28_SysCtrl.c file.
    InitSysCtrl();

// Initialise the physical pins of the DSP
    Gpio_select();

/* Initialize the CAN module */

    InitECan();

/* Write to the MSGID field - MBX number is written as its MSGID */
    ECanaMboxes.MBOX1.MSGID.all  = IDENTIFIER;  // extended identifier
    ECanaMboxes.MBOX1.MSGID.bit.IDE = 1;

/* Configure Mailbox 1 as Receiver mailbox */
    ECanaShadow.CANMD.all = ECanaRegs.CANMD.all;
    ECanaShadow.CANMD.bit.MD1 = 1;
    ECanaRegs.CANMD.all = ECanaShadow.CANMD.all;

/* Enable Mailbox 1  */

    ECanaShadow.CANME.all = ECanaRegs.CANME.all;
    ECanaShadow.CANME.bit.ME1 = 1;
    ECanaRegs.CANME.all = ECanaShadow.CANME.all;

/* Begin Receiving */
   while(1)
    {
     do {
        ECanaShadow.CANRMP.all = ECanaRegs.CANRMP.all;
        }
        while(ECanaShadow.CANRMP.bit.RMP1 != 1 );       // Wait for RMP1 to be set..

     ECanaShadow.CANRMP.bit.RMP1 = 1;
     ECanaRegs.CANRMP.all = ECanaShadow.CANRMP.all;    // Clear RMP1 bit and start again



    }

}

void Gpio_select(void)
{
    EALLOW;
    GpioCtrlRegs.GPAMUX1.all=0; //PORT A IS THE can PORT
    GpioCtrlRegs.GPAMUX2.all=0;
    GpioCtrlRegs.GPBMUX1.all=0;
       GpioCtrlRegs.GPBMUX2.all=0;


    GpioCtrlRegs.GPAMUX2.bit.GPIO19 = 3; // setting gpio19 as CANTXA
    GpioCtrlRegs.GPAMUX2.bit.GPIO18 = 3;  // setting gpio18 as CANRXA

    GpioCtrlRegs.GPADIR.all=0;       // GPIO PORTs  as input
    GpioCtrlRegs.GPBDIR.all=0x00ff;  // GPIO Port B15-B8 input , B7-B0 output
    GpioCtrlRegs.GPCDIR.all=0;


    GpioCtrlRegs.GPAQSEL1.all=0;          // Set GPIO input qualifier values
    GpioCtrlRegs.GPAQSEL2.all=0;

    GpioCtrlRegs.GPBQSEL1.all=0;
        GpioCtrlRegs.GPBQSEL2.all=0;



    GpioDataRegs.GPBDAT.all = 0x0000;   // Switch off LED's ( B7...B0)

    EDIS;
}

CAN-Tx

Fullscreen 3201.can-tx.txt Download

//
//      Lab CAN_1  : TMS320F2812
//      (C) Frank Bormann
//
//###########################################################################
//
// FILE:    Lab_CAN_1.c
//
// TITLE:   DSP28 CAN - Transmission with the Zwickau-adapterboard
//
//          Jumper JP4 :  2-3  ( 120 Ohm enabled)
//          Jumper JP5 :  1-2  ; Jumper JP6 _ 1-2 ( highspeed transceiver SN


//
//          Aim of the test :
//          Transmit the status of the 8 switches from GPIO - Port B15...B8
//          repeat the transmission every second
//          Mailbox 5 is used for transmission
//          Identifier : 0x1000 0000
//          DLC =  1
//
//          Frequency Osscillator : 30MHz
//          PLLCR = 0xA   :  multiply by 5
//          SYSCLKOUT = CLKIN = 150MHz
//          Highspeed - Prescaler (HISPCP = 0x0001; div by 2 ) : 75 Mhz
//          Lowspeed - Prescaler (LOSPCP  = 0x0002; div by 4 ) : 37.5 Mhz
//###########################################################################
//
//  Ver | dd mmm yyyy | Who  | Description of changes
// =====|=============|======|===============================================
//  1.0 | 09 May 2003 | F.B. | Startup Version for Lab_CAN_1
//  2.0 | 27 Nov 2003 | F.B. | adapted to header-files Version 1.00
//      |             |      |
//###########################################################################

// CAUTION :  DSP281x_ECan.h  , Version 1.0 ( Hareesh) contains an error
// the byte field of struct  CANMDL_BYTES and CANMDH_BYTES
// have the wrong order ( Byte1 to 4)instead of Byte 4 to 1)
// MODIFY  :  inside DSP281x_ECan.h modify the two structures to :
// struct  CANMDL_BYTES {      // bits   description
//   Uint16      BYTE3:8;     // 31:24
//   Uint16      BYTE2:8;     // 23:16
//   Uint16      BYTE1:8;     // 15:8
//   Uint16      BYTE0:8;     // 7:0
// };
//
// struct  CANMDH_BYTES {      // bits   description
//   Uint16      BYTE7:8;     // 63:56
//   Uint16      BYTE6:8;     // 55:48
//   Uint16      BYTE5:8;     // 47:40
//   Uint16      BYTE4:8;     // 39:32
// };
//##########################################################################

#include "DSP28x_Project.h"


#define IDENTIFIER 0x10000000

// Prototype statements for functions found within this file.

void Gpio_select(void);
void delay_loop();
Uint16 loopcount =0;
// Global Variables

/* Create a shadow register structure for the CAN control registers. This is
 needed, since, only 32-bit access is allowed to these registers. 16-bit access
 to these registers could potentially corrupt the register contents. This is
 especially true while writing to a bit (or group of bits) among bits 16 - 31 */

struct  ECAN_REGS ECanaShadow;

main()
{
// Initialize System Control registers, PLL, WatchDog, Clocks to default state:
// This function is found in the DSP28_SysCtrl.c file.
    InitSysCtrl();

// Initialise the physical pins of the DSP
    Gpio_select();

/* Initialize the CAN module */
    InitECan();

/* Write to the MSGID field  */

    ECanaMboxes.MBOX5.MSGID.all     = IDENTIFIER;
    ECanaMboxes.MBOX5.MSGID.bit.IDE = 1;  // Extended Identifier

/* Configure Mailbox under test as a Transmit mailbox */

    ECanaShadow.CANMD.all = ECanaRegs.CANMD.all;
    ECanaShadow.CANMD.bit.MD5 = 0;
    ECanaRegs.CANMD.all = ECanaShadow.CANMD.all;

/* Enable Mailbox under test */

    ECanaShadow.CANME.all = ECanaRegs.CANME.all;
    ECanaShadow.CANME.bit.ME5 = 1;
    ECanaRegs.CANME.all = ECanaShadow.CANME.all;

/* Write to DLC field in Master Control reg */

    ECanaMboxes.MBOX5.MSGCTRL.bit.DLC = 1;
    ECanaMboxes.MBOX5.MDL.all = 0x00000005;
      ECanaMboxes.MBOX5.MDH.all = 0x00000005;
/* Begin transmitting */


      for(;;)
      {
          ECanaShadow.CANTRS.all = 0;
          ECanaShadow.CANTRS.bit.TRS5 = 1;             // Set TRS for mailbox under test
          ECanaRegs.CANTRS.all = ECanaShadow.CANTRS.all;

          do
           {
           ECanaShadow.CANTA.all = ECanaRegs.CANTA.all;
           } while(ECanaShadow.CANTA.bit.TA5 == 0 );   // Wait for TA5 bit to be set..


          ECanaShadow.CANTA.all = 0;
          ECanaShadow.CANTA.bit.TA5 = 1;               // Clear TA5
          ECanaRegs.CANTA.all = ECanaShadow.CANTA.all;

          loopcount ++;
       }
        asm(" ESTOP0");  // Stop here

}

void Gpio_select(void)
{
    EALLOW;
    GpioCtrlRegs.GPAMUX1.all=0; //PORT A IS THE can PORT
    GpioCtrlRegs.GPAMUX2.all=0;
    GpioCtrlRegs.GPBMUX1.all=0;
       GpioCtrlRegs.GPBMUX2.all=0;


    GpioCtrlRegs.GPAMUX2.bit.GPIO19 = 3; // setting gpio19 as CANTXA
    GpioCtrlRegs.GPAMUX2.bit.GPIO18 = 3;  // setting gpio18 as CANRXA

    GpioCtrlRegs.GPADIR.all=0;       // GPIO PORTs  as input
    GpioCtrlRegs.GPBDIR.all=0x00ff;  // GPIO Port B15-B8 input , B7-B0 output
    GpioCtrlRegs.GPCDIR.all=0;


    GpioCtrlRegs.GPAQSEL1.all=0;          // Set GPIO input qualifier values
    GpioCtrlRegs.GPAQSEL2.all=0;

    GpioCtrlRegs.GPBQSEL1.all=0;
        GpioCtrlRegs.GPBQSEL2.all=0;



    GpioDataRegs.GPBDAT.all = 0x0000;   // Switch off LED's ( B7...B0)

    EDIS;
}

void delay_loop()
{
    long      i;
    for (i = 0; i < 10000000; i++) {}
}

over 10 years ago

0 Sneha Thakur over 10 years ago

Expert 2660 points

Can this problem be related to boot to SARAM? If yes how do we set it up?

Thanks Sneha

0 Sneha Thakur over 10 years ago in reply to Sneha Thakur

Expert 2660 points

I am trying to run eCANxmitA to eCANxmitB program given in the control suite.I can see the registers changing values at transmitter end..

1. But no transmission is being done as CANTA doesn't show any change..

2. I do not get toggle output at TXD pin oc CAN on F28335.It is constantly high.

3.Because of above reason I do not get the CANH and CANL waveforms and hence nothing at reciever end.

The program stops at the while loop waiting for TA(MBOX25)pin to get set..But as it is not transmiiting how will the reciever send acknowledgement???

Can someone please help me out with this?I am using ISO1050 EVM as CAN transciever and checking CAN Txd output on GPIO19.The Gpio pins have been programmed for this.

Please suggest a way out.

Thanks in advance

Sneha

0 Gautam Iyer over 10 years ago in reply to Sneha Thakur

Guru 192875 points

Hi Sneha,

I'm forwarding your query to an expert. Please be patient.

Regards,

Gautam

0 Sneha Thakur over 10 years ago in reply to Gautam Iyer

Expert 2660 points

Thanks alot Gauatm.

Sneha

0 Sneha Thakur over 10 years ago in reply to Sneha Thakur

Expert 2660 points

Can someone please get back to me on this??

I really need a way out of the issue.

Thanks

Sneha

0 Gautam Iyer over 10 years ago in reply to Sneha Thakur

Guru 192875 points

Forward

0 Sneha Thakur over 10 years ago in reply to Gautam Iyer

Expert 2660 points

I am still waiting for the people in TI forum to get back to me.Kindly hlep me solve the issue.

thanks and Regards

Sneha

0 Sneha Thakur over 10 years ago in reply to Sneha Thakur

Expert 2660 points

Is someone out there who can help me out with the CAN issue?

I am not able to get the CANH and CANL waveforms from eCAN xmit A to eCAN xmitB program given in control suite.

My CAN transceiver is working fine.

Today when I test the program for transmitter,I do get CANH and CANL but quite unnoticeable and that tooo not reliable,as in not appearing always when I run the program.

Please suggest the solution.

Thanks & Regards

Sneha

0 Adam Haun over 10 years ago in reply to Sneha Thakur

TI__Expert 8950 points

Sneha,

Can you try running the ecan_a_to_b_xmit example from controlSUITE? The code you're using now looks like it's intended for an F281x device.

Also, what is your hardware setup? Are you using two F2833s, one running the TX code and one running the RX code? Have you checked the CANBTC register to make sure it has a non-zero value?

0 Sneha Thakur over 10 years ago in reply to Adam Haun

Expert 2660 points

Hi Adam

Thanks for the reply.

1. I am running the code from control suite for eCAN-XmitA to eCAN-XmitB.In this CAN module A is Tx and CAN module B is Rx.Both are connected using ISO1050EVM (transciever in between) and DSP is F28335.

Issue with it:

No transmission- TXD pin continuously high,progarm is stuck at while waiting for CANTA to set.Hence can not expect to see CANH and CANL waveforms.
Program:

Fullscreen 6232.canxmitA to XmitB original.txt Download

// TI File $Revision: /main/2 $
// Checkin $Date: July 30, 2009   18:44:22 $
//###########################################################################
// Filename: Example_28xEcan_A_to_B_Xmit.c
//
// Description: eCAN-A To eCAN-B TXLOOP - Transmit loop
//
// ASSUMPTIONS:
//
//    This program requires the DSP2833x header files.
//
//    Both CAN ports of the 2833x DSP need to be connected
//    to each other (via CAN transceivers)0



//
//       eCANA is on GPIO31 (CANTXA)  and
//                   GPIO30 (CANRXA)
//
//       eCANB is on GPIO8  (CANTXB)  and
//                   GPIO10 (CANRXB)
//
//    As supplied, this project is configured for "boot to SARAM"
//    operation.  The 2833x Boot Mode table is shown below.
//    For information on configuring the boot mode of an eZdsp,
//    please refer to the documentation included with the eZdsp,
//
//       $Boot_Table:
//
//         GPIO87   GPIO86     GPIO85   GPIO84
//          XA15     XA14       XA13     XA12
//           PU       PU         PU       PU
//        ==========================================
//            1        1          1        1    Jump to Flash
//            1        1          1        0    SCI-A boot
//            1        1          0        1    SPI-A boot
//            1        1          0        0    I2C-A boot
//            1        0          1        1    eCAN-A boot
//            1        0          1        0    McBSP-A boot
//            1        0          0        1    Jump to XINTF x16
//            1        0          0        0    Jump to XINTF x32
//            0        1          1        1    Jump to OTP
//            0        1          1        0    Parallel GPIO I/O boot
//            0        1          0        1    Parallel XINTF boot
//            0        1          0        0    Jump to SARAM	    <- "boot to SARAM"
//            0        0          1        1    Branch to check boot mode
//            0        0          1        0    Boot to flash, bypass ADC cal
//            0        0          0        1    Boot to SARAM, bypass ADC cal
//            0        0          0        0    Boot to SCI-A, bypass ADC cal
//                                              Boot_Table_End$
//
// DESCRIPTION:
//
//    This example TRANSMITS data to another CAN module using MAILBOX5
//    This program could either loop forever or transmit "n" # of times,
//    where "n" is the TXCOUNT value.
//
//    This example can be used to check CAN-A and CAN-B. Since CAN-B is
//    initialized in DSP2833x_ECan.c, it will acknowledge all frames
//    transmitted by the node on which this code runs. Both CAN ports of
//    the 2833x DSP need to be connected to each other (via CAN transceivers)
//
//###########################################################################
// Original Author: HJ
//
// $TI Release: 2833x/2823x Header Files V1.32 $
// $Release Date: June 28, 2010 $
//###########################################################################

#include "DSP28x_Project.h"     // Device Headerfile and Examples Include File

#define TXCOUNT  100  // Transmission will take place (TXCOUNT) times..

// Globals for this example
long      i;
long 	  loopcount = 0;


void main()
{

/* Create a shadow register structure for the CAN control registers. This is
 needed, since, only 32-bit access is allowed to these registers. 16-bit access
 to these registers could potentially corrupt the register contents. This is
 especially true while writing to a bit (or group of bits) among bits 16 - 31 */

   struct ECAN_REGS ECanaShadow;

// Step 1. Initialize System Control:
// PLL, WatchDog, enable Peripheral Clocks
// This example function is found in the DSP2833x_SysCtrl.c file.
   InitSysCtrl();

// Step 2. Initalize GPIO:
// This example function is found in the DSP2833x_Gpio.c file and
// illustrates how to set the GPIO to it's default state.
// InitGpio();  // Skipped for this example

   // Just initalize eCAN pins for this example
   // This function is in DSP2833x_ECan.c
   InitECanGpio();

// Step 3. Clear all interrupts and initialize PIE vector table:
// Disable CPU interrupts
   DINT;

// Initialize the PIE control registers to their default state.
// The default state is all PIE interrupts disabled and flags
// are cleared.
// This function is found in the DSP2833x_PieCtrl.c file.
   InitPieCtrl();

// Disable CPU interrupts and clear all CPU interrupt flags:
   IER = 0x0000;
   IFR = 0x0000;

// Initialize the PIE vector table with pointers to the shell Interrupt
// Service Routines (ISR).
// This will populate the entire table, even if the interrupt
// is not used in this example.  This is useful for debug purposes.
// The shell ISR routines are found in DSP2833x_DefaultIsr.c.
// This function is found in DSP2833x_PieVect.c.
   InitPieVectTable();

// Interrupts that are used in this example are re-mapped to
// ISR functions found within this file.

// No interrupts used in this example.

// Step 4. Initialize all the Device Peripherals:
// This function is found in DSP2833x_InitPeripherals.c
// InitPeripherals(); // Not required for this example

   // In this case just initalize eCAN-A and eCAN-B
   // This function is in DSP2833x_ECan.c
   InitECan();

// Step 5. User specific code:

/* Write to the MSGID field  */

   ECanaMboxes.MBOX25.MSGID.all = 0x95555555; // Extended Identifier

/* Configure Mailbox under test as a Transmit mailbox */

   ECanaShadow.CANMD.all = ECanaRegs.CANMD.all;
   ECanaShadow.CANMD.bit.MD25 = 0;
   ECanaRegs.CANMD.all = ECanaShadow.CANMD.all;

/* Enable Mailbox under test */

   ECanaShadow.CANME.all = ECanaRegs.CANME.all;
   ECanaShadow.CANME.bit.ME25 = 1;
   ECanaRegs.CANME.all = ECanaShadow.CANME.all;

/* Write to DLC field in Master Control reg */

   ECanaMboxes.MBOX25.MSGCTRL.bit.DLC = 8;

/* Write to the mailbox RAM field */

   ECanaMboxes.MBOX25.MDL.all = 0x55555555;
   ECanaMboxes.MBOX25.MDH.all = 0x55555555;

/* Begin transmitting */


   for(i=0; i < TXCOUNT; i++)
   {
       ECanaShadow.CANTRS.all = 0;
       ECanaShadow.CANTRS.bit.TRS25 = 1;             // Set TRS for mailbox under test
       ECanaRegs.CANTRS.all = ECanaShadow.CANTRS.all;

       do
    	{
      	ECanaShadow.CANTA.all = ECanaRegs.CANTA.all;
    	} while(ECanaShadow.CANTA.bit.TA25 == 0 );   // Wait for TA5 bit to be set..


       ECanaShadow.CANTA.all = 0;
       ECanaShadow.CANTA.bit.TA25 = 1;     	         // Clear TA5
       ECanaRegs.CANTA.all = ECanaShadow.CANTA.all;

       loopcount ++;
    }
     asm(" ESTOP0");  // Stop here
}

2. I am also trying to transmit data from MBX5 eCAN of DSP1 to MBX1 eCAN of DSP2.(DSP used - F28335).The codes are:

Fullscreen 8255.CAN-tx-MBOX5.txt Download

// TI File $Revision: /main/2 $
// Checkin $Date: July 30, 2009   18:44:22 $
//###########################################################################
// Filename: Example_28xEcan_A_to_B_Xmit.c
//
// Description: eCANA-1 to eCANA2 Transmit loop
//
// ASSUMPTIONS:
//
//    This program requires the DSP2833x header files.
//
//    The CAN ports A of the two 2833x DSP need to be connected
//    to each other (via CAN transceivers)0



//
//      Transmitter end- eCANA1 is on GPIO19 (CANTXA)  and
//                   GPIO18 (CANRXA)
//
//    Reciever end-  eCANA2 is on GPIO19  (CANTXB)  and
//                   GPIO18 (CANRXB)
//
//    As supplied, this project is configured for "boot to SARAM"
//    operation.  The 2833x Boot Mode table is shown below.
//    For information on configuring the boot mode of an eZdsp,
//    please refer to the documentation included with the eZdsp,
//
//       $Boot_Table:
//
//         GPIO87   GPIO86     GPIO85   GPIO84
//          XA15     XA14       XA13     XA12
//           PU       PU         PU       PU
//        ==========================================
//            1        1          1        1    Jump to Flash
//            1        1          1        0    SCI-A boot
//            1        1          0        1    SPI-A boot
//            1        1          0        0    I2C-A boot
//            1        0          1        1    eCAN-A boot
//            1        0          1        0    McBSP-A boot
//            1        0          0        1    Jump to XINTF x16
//            1        0          0        0    Jump to XINTF x32
//            0        1          1        1    Jump to OTP
//            0        1          1        0    Parallel GPIO I/O boot
//            0        1          0        1    Parallel XINTF boot
//            0        1          0        0    Jump to SARAM       <- "boot to SARAM"
//            0        0          1        1    Branch to check boot mode
//            0        0          1        0    Boot to flash, bypass ADC cal
//            0        0          0        1    Boot to SARAM, bypass ADC cal
//            0        0          0        0    Boot to SCI-A, bypass ADC cal
//                                              Boot_Table_End$
//
// DESCRIPTION:
//
//    This example TRANSMITS data from MAILBOX5, CANA on DSP1 to another DS2P CANA module MAILBOX1
//    This program could either loop forever or transmit "n" # of times,
//    where "n" is the TXCOUNT value.
//
// ###########################################################################

#include "DSP28x_Project.h"

// Prototype statements for functions found within this file.

Uint16 loopcount =0;
// Global Variables

/* Create a shadow register structure for the CAN control registers. This is
 needed, since, only 32-bit access is allowed to these registers. 16-bit access
 to these registers could potentially corrupt the register contents. This is
 especially true while writing to a bit (or group of bits) among bits 16 - 31 */

struct  ECAN_REGS ECanaShadow;

main()
{
// Initialize System Control registers, PLL, WatchDog, Clocks to default state:
// This function is found in the DSP28_SysCtrl.c file.
    InitSysCtrl();

// Initialise the physical pins of the DSP
   //* Initialize the CAN module */
    InitECan();

/* Write to the MSGID field  */

    ECanaMboxes.MBOX5.MSGID.all     = 0x11111111;
    ECanaMboxes.MBOX5.MSGID.bit.IDE = 1;  // Extended Identifier

/* Configure Mailbox under test as a Transmit mailbox */

    ECanaShadow.CANMD.all = ECanaRegs.CANMD.all;
    ECanaShadow.CANMD.bit.MD5 = 0;
    ECanaRegs.CANMD.all = ECanaShadow.CANMD.all;

/* Enable Mailbox under test */

    ECanaShadow.CANME.all = ECanaRegs.CANME.all;
    ECanaShadow.CANME.bit.ME5 = 1;
    ECanaRegs.CANME.all = ECanaShadow.CANME.all;

/* Write to DLC field in Master Control reg */

    ECanaMboxes.MBOX5.MSGCTRL.bit.DLC = 1;
    ECanaMboxes.MBOX5.MDL.all = 0x00000005;
      ECanaMboxes.MBOX5.MDH.all = 0x00000005;
/* Begin transmitting */


      for(;;)
      {
          ECanaShadow.CANTRS.all = 0;
          ECanaShadow.CANTRS.bit.TRS5 = 1;             // Set TRS for mailbox under test
          ECanaRegs.CANTRS.all = ECanaShadow.CANTRS.all;

          do
           {
           ECanaShadow.CANTA.all = ECanaRegs.CANTA.all;
           } while(ECanaShadow.CANTA.bit.TA5 == 0 );   // Wait for TA5 bit to be set..


          ECanaShadow.CANTA.all = 0;
          ECanaShadow.CANTA.bit.TA5 = 1;               // Clear TA5
          ECanaRegs.CANTA.all = ECanaShadow.CANTA.all;

          loopcount ++;
       }
        asm(" ESTOP0");  // Stop here

}

Fullscreen 6278.CAN-rx-MBOX1.txt Download

// TI File $Revision: /main/2 $
// Checkin $Date: July 30, 2009   18:44:22 $
//###########################################################################
// Filename: Example_28xEcan_A_to_B_Xmit.c
//
// Description: eCANA-1 to eCANA2 Transmit loop
//
// ASSUMPTIONS:
//
//    This program requires the DSP2833x header files.
//
//    The CAN ports A of the two 2833x DSP need to be connected
//    to each other (via CAN transceivers)0



//
//      Transmitter end- eCANA1 is on GPIO19 (CANTXA)  and
//                   GPIO18 (CANRXA)
//
//    Reciever end-  eCANA2 is on GPIO19  (CANTXB)  and
//                   GPIO18 (CANRXB)
//
//    As supplied, this project is configured for "boot to SARAM"
//    operation.  The 2833x Boot Mode table is shown below.
//    For information on configuring the boot mode of an eZdsp,
//    please refer to the documentation included with the eZdsp,
//
//       $Boot_Table:
//
//         GPIO87   GPIO86     GPIO85   GPIO84
//          XA15     XA14       XA13     XA12
//           PU       PU         PU       PU
//        ==========================================
//            1        1          1        1    Jump to Flash
//            1        1          1        0    SCI-A boot
//            1        1          0        1    SPI-A boot
//            1        1          0        0    I2C-A boot
//            1        0          1        1    eCAN-A boot
//            1        0          1        0    McBSP-A boot
//            1        0          0        1    Jump to XINTF x16
//            1        0          0        0    Jump to XINTF x32
//            0        1          1        1    Jump to OTP
//            0        1          1        0    Parallel GPIO I/O boot
//            0        1          0        1    Parallel XINTF boot
//            0        1          0        0    Jump to SARAM       <- "boot to SARAM"
//            0        0          1        1    Branch to check boot mode
//            0        0          1        0    Boot to flash, bypass ADC cal
//            0        0          0        1    Boot to SARAM, bypass ADC cal
//            0        0          0        0    Boot to SCI-A, bypass ADC cal
//                                              Boot_Table_End$
//
// DESCRIPTION:
//
//    This example TRANSMITS data from MAILBOX5, CANA on DSP1 to another DS2P CANA module MAILBOX1
//    This program could either loop forever or transmit "n" # of times,
//    where "n" is the TXCOUNT value.
//
// ###########################################################################

#include "DSP28x_Project.h"

// Prototype statements for functions found within this file.

// Global Variables

/* Create a shadow register structure for the CAN control registers. This is
 needed, since, only 32-bit access is allowed to these registers. 16-bit access
 to these registers could potentially corrupt the register contents. This is
 especially true while writing to a bit (or group of bits) among bits 16 - 31 */

struct  ECAN_REGS ECanaShadow;

main()
{
// Initialize System Control registers, PLL, WatchDog, Clocks to default state:
// This function is found in the DSP28_SysCtrl.c file.
    InitSysCtrl();

// Initialise the physical pins of the DSP
    //* Initialize the CAN module */

    InitECan();

/* Write to the MSGID field - MBX number is written as its MSGID */
    ECanaMboxes.MBOX1.MSGID.all  = 0x11111111;  // extended identifier
    ECanaMboxes.MBOX1.MSGID.bit.IDE = 1;

/* Configure Mailbox 1 as Receiver mailbox */
    ECanaShadow.CANMD.all = ECanaRegs.CANMD.all;
    ECanaShadow.CANMD.bit.MD1 = 1;
    ECanaRegs.CANMD.all = ECanaShadow.CANMD.all;
    ECanaMboxes.MBOX1.MSGCTRL.all  = 0;

    ECanaMboxes.MBOX1.MSGCTRL.bit.DLC = 2;
/* Enable Mailbox 1  */

    ECanaShadow.CANME.all = ECanaRegs.CANME.all;
    ECanaShadow.CANME.bit.ME1 = 1;
    ECanaRegs.CANME.all = ECanaShadow.CANME.all;

/* Begin Receiving */
   while(1)
    {
     do {
        ECanaShadow.CANRMP.all = ECanaRegs.CANRMP.all;
        }
        while(ECanaShadow.CANRMP.bit.RMP1 != 1 );       // Wait for RMP1 to be set..

     ECanaShadow.CANRMP.bit.RMP1 = 1;
     ECanaRegs.CANRMP.all = ECanaShadow.CANRMP.all;    // Clear RMP1 bit and start again



    }

}

In this also I face the same issues as previous one,No toggle output on TXD pin.

3.I have checked my ISO1050EVM it is working fine and giving CANH and CANL waveforms when input is a high frequency pulse.

4. CANBTC for the program1 is000400D2.

Thanks

Sneha

0 Sneha Thakur over 10 years ago in reply to Sneha Thakur

Expert 2660 points

Hi Adam

There is one more issue which I am facing now.When I run this program 1 i.e eCAN xmit A to eCAN xmit B on same DSP F28335 but different modules,I can get CANH-CANL waveforms at the first attempt i.e. checking those before giving it to receiver end.

But the frequency here is 2.5 kHz which according to me should be 1MHz as bit rate for CAN is set as 1 Mbps.

Now the real problem arises,i.e. if I halt the program or terminate it and then debug it again,I do not get these waveforms.Instead i get continuous high output.To get these waveforms again I have to shut down everything and then wait for some minimum amount of time and then the issue repeats like this again and again.

Thanks

Sneha

0 Adam Haun over 10 years ago in reply to Sneha Thakur

TI__Expert 8950 points

Sneha,

I tried your code with the v133 device support files from controlSUITE and saw correct-looking activity on the TX pin. I was able to cause brief pulses like what you see by disconnecting CANRX. Please make sure that your CANTX pin feeds back in CANRX, either directly (for testing) or by connecting them both to the transceiver.

Thanks,

0 Sneha Thakur over 10 years ago in reply to Adam Haun

Expert 2660 points

Hi Adam

Thanks for your time.

I was trying some or the other thing with the code.And what I have observed is:

1. The pulses are for brief time as TxCOUNT =100,so loop runs for 100 times.If I put it into forever loop it gives continuous pulses.

2. Error bits in CANES get set at times,I observed BE,SE bit =1 at times.

3. If this is the correct output then why is not this reliable as in after terminating the program or halting why do we have to wait for some time to again get the pulses?

4. I tried it once with full connection: Tx- Transciever-Transceiver - Rx, But I couldn;t observe any change in receiver registers.How can I confirm with my full connection that CAN communication is working?

I am really thankful for the time you areputting in for this.

Thanks & Regards

SNeha

0 Adam Haun over 10 years ago in reply to Sneha Thakur

TI__Expert 8950 points

Sneha,

The BE bit indicates that the CAN module is not receiving the same data that it's sending. This probably means that your CANARX pin is not connected correctly. You need to use both the TX and RX pins on both MCUs. For a quick test, try shorting GPIOs 18 and 19 together and disconnect the transceiver.

The output stops when the module detects lots of errors. The CAN protocol says that after a certain number of errors the transmitter has to drop off the bus. You can set the ABO bit in CANMC to make the transmitter come back online automatically.

0 Sneha Thakur over 10 years ago in reply to Adam Haun

Expert 2660 points

HI Adam

ABO setting in CANMC doesn't help.
I had one doubt when I check the control suite eCAN A-B xmit program with tx-transcievers-Rx connected,what I get at the RXD pin of other can module is constant high pulse.Is this correct?
Hence to verify this I was not connecting RX and only checking CANH and CANL waveforms,But then I am not getting them.

Please suggest something.
Thanks
Sneha

0 Adam Haun over 10 years ago in reply to Sneha Thakur

TI__Expert 8950 points

The RX and TX pins on both modules need to be connected to the bus. If they're constant high, something is wrong with your connection.

0 Sneha Thakur over 10 years ago in reply to Adam Haun

Expert 2660 points

Hi Adam

oki I will try testing with both Rx and Tx connected. But then how do I confirm If the communication is actually working.

Thanks
Sneha

0 Adam Haun over 10 years ago in reply to Sneha Thakur

TI__Expert 8950 points

You can scope one of the TX pins. CAN has a pretty distinctive waveform:

http://fplreflib.findlay.co.uk/articles/22612/fig2.jpg

Alternately, you can check the received data, or the status bits in the module.

0 Sneha Thakur over 10 years ago in reply to Adam Haun

Expert 2660 points

Thanks Adam.
i will update you soon.

regards
sneha

0 Sneha Thakur over 10 years ago in reply to Sneha Thakur

Expert 2660 points

Hi Adam

As per your suggestion I connected both Tx and Rx pins and ran the program but in vain.

No communication is taking place.

my hardware works fine when given a high pulse input to TXD pin of EVM,but when the CAN program is run it leads to running.At resent I am transferring from MBOx1 of eCANA on DSP-1 to MBOX2 of eCANB on DSP-2, bit rate 125 kbps.

1.can tx

Fullscreen 5875.CANtx-MBOX1.txt Download

// TI File $Revision: /main/2 $
// Checkin $Date: July 30, 2009   18:44:22 $
//###########################################################################
// Filename: Example_28xEcan_A_to_B_Xmit.c
//
// Description: eCANA-1 to eCANA2 Transmit loop
//
// ASSUMPTIONS:
//
//    This program requires the DSP2833x header files.
//
//    The CAN ports A of the two 2833x DSP need to be connected
//    to each other (via CAN transceivers)0



//
//      Transmitter end- eCANA1 is on GPIO19 (CANTXA)  and
//                   GPIO18 (CANRXA)
//
//    Reciever end-  eCANA2 is on GPIO19  (CANTXB)  and
//                   GPIO18 (CANRXB)
//
//    As supplied, this project is configured for "boot to SARAM"
//    operation.  The 2833x Boot Mode table is shown below.
//    For information on configuring the boot mode of an eZdsp,
//    please refer to the documentation included with the eZdsp,
//
//       $Boot_Table:
//
//         GPIO87   GPIO86     GPIO85   GPIO84
//          XA15     XA14       XA13     XA12
//           PU       PU         PU       PU
//        ==========================================
//            1        1          1        1    Jump to Flash
//            1        1          1        0    SCI-A boot
//            1        1          0        1    SPI-A boot
//            1        1          0        0    I2C-A boot
//            1        0          1        1    eCAN-A boot
//            1        0          1        0    McBSP-A boot
//            1        0          0        1    Jump to XINTF x16
//            1        0          0        0    Jump to XINTF x32
//            0        1          1        1    Jump to OTP
//            0        1          1        0    Parallel GPIO I/O boot
//            0        1          0        1    Parallel XINTF boot
//            0        1          0        0    Jump to SARAM       <- "boot to SARAM"
//            0        0          1        1    Branch to check boot mode
//            0        0          1        0    Boot to flash, bypass ADC cal
//            0        0          0        1    Boot to SARAM, bypass ADC cal
//            0        0          0        0    Boot to SCI-A, bypass ADC cal
//                                              Boot_Table_End$
//
// DESCRIPTION:
//
//    This example TRANSMITS data from MAILBOX5, CANA on DSP1 to another DS2P CANA module MAILBOX1
//    This program could either loop forever or transmit "n" # of times,
//    where "n" is the TXCOUNT value.
//
// ###########################################################################

#include "DSP28x_Project.h"

// Prototype statements for functions found within this file.

Uint16 loopcount =0;
// Global Variables

/* Create a shadow register structure for the CAN control registers. This is
 needed, since, only 32-bit access is allowed to these registers. 16-bit access
 to these registers could potentially corrupt the register contents. This is
 especially true while writing to a bit (or group of bits) among bits 16 - 31 */

struct  ECAN_REGS ECanaShadow;

main()
{
// Initialize System Control registers, PLL, WatchDog, Clocks to default state:
// This function is found in the DSP28_SysCtrl.c file.
    InitSysCtrl();

// Initialise the physical pins of the DSP
   //* Initialize the CAN module */
    InitECan();

/* Write to the MSGID field  */

    ECanaMboxes.MBOX1.MSGID.all     = 0x00050000;
    ECanaMboxes.MBOX1.MSGID.bit.IDE = 0;  // standard Identifier

/* Configure Mailbox under test as a Transmit mailbox */

    ECanaShadow.CANMD.all = ECanaRegs.CANMD.all;
    ECanaShadow.CANMD.bit.MD1 = 0;
    ECanaRegs.CANMD.all = ECanaShadow.CANMD.all;

/* Enable Mailbox under test */

    ECanaShadow.CANME.all = ECanaRegs.CANME.all;
    ECanaShadow.CANME.bit.ME1 = 1;
    ECanaRegs.CANME.all = ECanaShadow.CANME.all;

/* Write to DLC field in Master Control reg */

        ECanaMboxes.MBOX1.MSGCTRL.bit.DLC = 8;
    ECanaMboxes.MBOX1.MDL.all = 0x0000008A;
    ECanaMboxes.MBOX1.MDH.all = 0x0000008A;

/* Begin transmitting */


      for(;;)
      {
          ECanaShadow.CANTRS.all = 0;
          ECanaShadow.CANTRS.bit.TRS1 = 1;             // Set TRS for mailbox under test
          ECanaRegs.CANTRS.all = ECanaShadow.CANTRS.all;

          do
           {
           ECanaShadow.CANTA.all = ECanaRegs.CANTA.all;
           } while(ECanaShadow.CANTA.bit.TA1 == 0 );   // Wait for TA5 bit to be set..


          ECanaShadow.CANTA.all = 0;
          ECanaShadow.CANTA.bit.TA1 = 1;               // Clear TA5
          ECanaRegs.CANTA.all = ECanaShadow.CANTA.all;

          loopcount ++;
       }
        asm(" ESTOP0");  // Stop here

}

2.can tx.c

Fullscreen 8508.TX_intialisation.txt Download

// TI File $Revision: /main/8 $
// Checkin $Date: June 25, 2008   15:19:07 $
//###########################################################################
//
// FILE:	DSP2833x_ECan.c
//
// TITLE:	DSP2833x Enhanced CAN Initialization & Support Functions.
//
//###########################################################################
// $TI Release: 2833x/2823x Header Files V1.32 $
// $Release Date: June 28, 2010 $
//###########################################################################

#include "DSP2833x_Device.h"     // DSP2833x Headerfile Include File
#include "DSP2833x_Examples.h"   // DSP2833x Examples Include File


//---------------------------------------------------------------------------
// InitECan:
//---------------------------------------------------------------------------
// This function initializes the eCAN module to a known state.
//
void InitECan(void)
{
   InitECana();
#if DSP28_ECANB
   InitECanb();
#endif // if DSP28_ECANB
}

void InitECana(void)		// Initialize eCAN-A module
{
/* Create a shadow register structure for the CAN control registers. This is
 needed, since only 32-bit access is allowed to these registers. 16-bit access
 to these registers could potentially corrupt the register contents or return
 false data. This is especially true while writing to/reading from a bit
 (or group of bits) among bits 16 - 31 */

struct ECAN_REGS ECanaShadow;

	EALLOW;		// EALLOW enables access to protected bits

/* Configure eCAN RX and TX pins for CAN operation using eCAN regs*/

    ECanaShadow.CANTIOC.all = ECanaRegs.CANTIOC.all;
    ECanaShadow.CANTIOC.bit.TXFUNC = 1;
    ECanaRegs.CANTIOC.all = ECanaShadow.CANTIOC.all;

    ECanaShadow.CANRIOC.all = ECanaRegs.CANRIOC.all;
    ECanaShadow.CANRIOC.bit.RXFUNC = 1;
    ECanaRegs.CANRIOC.all = ECanaShadow.CANRIOC.all;

/* Configure eCAN for SCC mode - (reqd to access mailboxes 0 to 15) */
									

	ECanaShadow.CANMC.all = ECanaRegs.CANMC.all;
	ECanaShadow.CANMC.bit.SCB = 0;
	ECanaRegs.CANMC.all = ECanaShadow.CANMC.all;

/* Initialize all bits of 'Master Control Field' to zero */
// Some bits of MSGCTRL register come up in an unknown state. For proper operation,
// all bits (including reserved bits) of MSGCTRL must be initialized to zero

    //ECanaMboxes.MBOX0.MSGCTRL.all = 0x00000000;
    ECanaMboxes.MBOX1.MSGCTRL.all = 0x00000000;
   // ECanaMboxes.MBOX2.MSGCTRL.all = 0x00000000;
   // ECanaMboxes.MBOX3.MSGCTRL.all = 0x00000000;
    //ECanaMboxes.MBOX4.MSGCTRL.all = 0x00000000;
   // ECanaMboxes.MBOX5.MSGCTRL.all = 0x00000000;
    //ECanaMboxes.MBOX6.MSGCTRL.all = 0x00000000;
    //ECanaMboxes.MBOX7.MSGCTRL.all = 0x00000000;
   // ECanaMboxes.MBOX8.MSGCTRL.all = 0x00000000;
   // ECanaMboxes.MBOX9.MSGCTRL.all = 0x00000000;
   // ECanaMboxes.MBOX10.MSGCTRL.all = 0x00000000;
   // ECanaMboxes.MBOX11.MSGCTRL.all = 0x00000000;
   // ECanaMboxes.MBOX12.MSGCTRL.all = 0x00000000;
   // ECanaMboxes.MBOX13.MSGCTRL.all = 0x00000000;
   // ECanaMboxes.MBOX14.MSGCTRL.all = 0x00000000;
   // ECanaMboxes.MBOX15.MSGCTRL.all = 0x00000000;
    //ECanaMboxes.MBOX16.MSGCTRL.all = 0x00000000;
    //ECanaMboxes.MBOX17.MSGCTRL.all = 0x00000000;
 //   ECanaMboxes.MBOX18.MSGCTRL.all = 0x00000000;
    //ECanaMboxes.MBOX19.MSGCTRL.all = 0x00000000;
   // ECanaMboxes.MBOX20.MSGCTRL.all = 0x00000000;
   // ECanaMboxes.MBOX21.MSGCTRL.all = 0x00000000;
   // ECanaMboxes.MBOX22.MSGCTRL.all = 0x00000000;
 //   ECanaMboxes.MBOX23.MSGCTRL.all = 0x00000000;
  //  ECanaMboxes.MBOX24.MSGCTRL.all = 0x00000000;
  //  ECanaMboxes.MBOX25.MSGCTRL.all = 0x00000000;
   // ECanaMboxes.MBOX26.MSGCTRL.all = 0x00000000;
   // ECanaMboxes.MBOX27.MSGCTRL.all = 0x00000000;
   // ECanaMboxes.MBOX28.MSGCTRL.all = 0x00000000;
   // ECanaMboxes.MBOX29.MSGCTRL.all = 0x00000000;
   // ECanaMboxes.MBOX30.MSGCTRL.all = 0x00000000;
   // ECanaMboxes.MBOX31.MSGCTRL.all = 0x00000000;

// TAn, RMPn, GIFn bits are all zero upon reset and are cleared again
//	as a matter of precaution.

	ECanaRegs.CANTA.bit.TA1 = 1 ;	/* Clear all TA1 bits */

//	ECanaRegs.CANRMP.bit.RMP1 = 1;	/* Clear all RMPn bits */

	ECanaRegs.CANGIF0.all = 0xFFFFFFFF;	/* Clear all interrupt flag bits */
	ECanaRegs.CANGIF1.all = 0xFFFFFFFF;


/* Configure bit timing parameters for eCANA*/
	ECanaShadow.CANMC.all = ECanaRegs.CANMC.all;
	ECanaShadow.CANMC.bit.CCR = 1 ;            // Set CCR = 1
    ECanaRegs.CANMC.all = ECanaShadow.CANMC.all;

    ECanaShadow.CANES.all = ECanaRegs.CANES.all;

    do
	{
	    ECanaShadow.CANES.all = ECanaRegs.CANES.all;
    } while(ECanaShadow.CANES.bit.CCE != 1 );  		// Wait for CCE bit to be set..

    ECanaShadow.CANBTC.all = 0;

    #if (CPU_FRQ_150MHZ)                       // CPU_FRQ_150MHz is defined in DSP2833x_Examples.h
		/* The following block for all 150 MHz SYSCLKOUT (75 MHz CAN clock) - default. Bit rate = 1 Mbps
		   See Note at End of File */
			ECanaShadow.CANBTC.bit.BRPREG = 39;
			ECanaShadow.CANBTC.bit.TSEG2REG = 2;
			ECanaShadow.CANBTC.bit.TSEG1REG = 10;
    #endif
	#if (CPU_FRQ_100MHZ)                       // CPU_FRQ_100MHz is defined in DSP2833x_Examples.h
	/* The following block is only for 100 MHz SYSCLKOUT (50 MHz CAN clock). Bit rate = 1 Mbps
	   See Note at End of File */
	    ECanaShadow.CANBTC.bit.BRPREG = 4;
		ECanaShadow.CANBTC.bit.TSEG2REG = 1;
		ECanaShadow.CANBTC.bit.TSEG1REG = 6;
	#endif


    ECanaShadow.CANBTC.bit.SAM = 1;
    ECanaRegs.CANBTC.all = ECanaShadow.CANBTC.all;

    ECanaShadow.CANMC.all = ECanaRegs.CANMC.all;
	ECanaShadow.CANMC.bit.CCR = 0 ;            // Set CCR = 0
    ECanaRegs.CANMC.all = ECanaShadow.CANMC.all;

    ECanaShadow.CANES.all = ECanaRegs.CANES.all;

    do
    {
       ECanaShadow.CANES.all = ECanaRegs.CANES.all;
    } while(ECanaShadow.CANES.bit.CCE != 0 ); 		// Wait for CCE bit to be  cleared..

/* Disable all Mailboxes  */
 	ECanaRegs.CANME.all = 0;		// Required before writing the MSGIDs

    EDIS;
}


#if (DSP28_ECANB)
void InitECanb(void)		// Initialize eCAN-B module
{
/* Create a shadow register structure for the CAN control registers. This is
 needed, since only 32-bit access is allowed to these registers. 16-bit access
 to these registers could potentially corrupt the register contents or return
 false data. This is especially true while writing to/reading from a bit
 (or group of bits) among bits 16 - 31 */

struct ECAN_REGS ECanbShadow;

   EALLOW;		// EALLOW enables access to protected bits

/* Configure eCAN RX and TX pins for CAN operation using eCAN regs*/

    ECanbShadow.CANTIOC.all = ECanbRegs.CANTIOC.all;
    ECanbShadow.CANTIOC.bit.TXFUNC = 1;
    ECanbRegs.CANTIOC.all = ECanbShadow.CANTIOC.all;

    ECanbShadow.CANRIOC.all = ECanbRegs.CANRIOC.all;
    ECanbShadow.CANRIOC.bit.RXFUNC = 1;
    ECanbRegs.CANRIOC.all = ECanbShadow.CANRIOC.all;

/* Configure eCAN for HECC mode - (reqd to access mailboxes 16 thru 31) */

	ECanbShadow.CANMC.all = ECanbRegs.CANMC.all;
	ECanbShadow.CANMC.bit.SCB = 1;
	ECanbRegs.CANMC.all = ECanbShadow.CANMC.all;

/* Initialize all bits of 'Master Control Field' to zero */
// Some bits of MSGCTRL register come up in an unknown state. For proper operation,
// all bits (including reserved bits) of MSGCTRL must be initialized to zero

    ECanbMboxes.MBOX0.MSGCTRL.all = 0x00000000;
    ECanbMboxes.MBOX1.MSGCTRL.all = 0x00000000;
    ECanbMboxes.MBOX2.MSGCTRL.all = 0x00000000;
    ECanbMboxes.MBOX3.MSGCTRL.all = 0x00000000;
    ECanbMboxes.MBOX4.MSGCTRL.all = 0x00000000;
    ECanbMboxes.MBOX5.MSGCTRL.all = 0x00000000;
    ECanbMboxes.MBOX6.MSGCTRL.all = 0x00000000;
    ECanbMboxes.MBOX7.MSGCTRL.all = 0x00000000;
    ECanbMboxes.MBOX8.MSGCTRL.all = 0x00000000;
    ECanbMboxes.MBOX9.MSGCTRL.all = 0x00000000;
    ECanbMboxes.MBOX10.MSGCTRL.all = 0x00000000;
    ECanbMboxes.MBOX11.MSGCTRL.all = 0x00000000;
    ECanbMboxes.MBOX12.MSGCTRL.all = 0x00000000;
    ECanbMboxes.MBOX13.MSGCTRL.all = 0x00000000;
    ECanbMboxes.MBOX14.MSGCTRL.all = 0x00000000;
    ECanbMboxes.MBOX15.MSGCTRL.all = 0x00000000;
    ECanbMboxes.MBOX16.MSGCTRL.all = 0x00000000;
    ECanbMboxes.MBOX17.MSGCTRL.all = 0x00000000;
    ECanbMboxes.MBOX18.MSGCTRL.all = 0x00000000;
    ECanbMboxes.MBOX19.MSGCTRL.all = 0x00000000;
    ECanbMboxes.MBOX20.MSGCTRL.all = 0x00000000;
    ECanbMboxes.MBOX21.MSGCTRL.all = 0x00000000;
    ECanbMboxes.MBOX22.MSGCTRL.all = 0x00000000;
    ECanbMboxes.MBOX23.MSGCTRL.all = 0x00000000;
    ECanbMboxes.MBOX24.MSGCTRL.all = 0x00000000;
    ECanbMboxes.MBOX25.MSGCTRL.all = 0x00000000;
    ECanbMboxes.MBOX26.MSGCTRL.all = 0x00000000;
    ECanbMboxes.MBOX27.MSGCTRL.all = 0x00000000;
    ECanbMboxes.MBOX28.MSGCTRL.all = 0x00000000;
    ECanbMboxes.MBOX29.MSGCTRL.all = 0x00000000;
    ECanbMboxes.MBOX30.MSGCTRL.all = 0x00000000;
    ECanbMboxes.MBOX31.MSGCTRL.all = 0x00000000;

// TAn, RMPn, GIFn bits are all zero upon reset and are cleared again
//	as a matter of precaution.

	ECanbRegs.CANTA.all	= 0xFFFFFFFF;	/* Clear all TAn bits */

	ECanbRegs.CANRMP.all = 0xFFFFFFFF;	/* Clear all RMPn bits */

	ECanbRegs.CANGIF0.all = 0xFFFFFFFF;	/* Clear all interrupt flag bits */
	ECanbRegs.CANGIF1.all = 0xFFFFFFFF;


/* Configure bit timing parameters for eCANB*/

	ECanbShadow.CANMC.all = ECanbRegs.CANMC.all;
	ECanbShadow.CANMC.bit.CCR = 1 ;            // Set CCR = 1
    ECanbRegs.CANMC.all = ECanbShadow.CANMC.all;

    ECanbShadow.CANES.all = ECanbRegs.CANES.all;

    do
	{
	    ECanbShadow.CANES.all = ECanbRegs.CANES.all;
	} while(ECanbShadow.CANES.bit.CCE != 1 ); 		// Wait for CCE bit to be  cleared..


    ECanbShadow.CANBTC.all = 0;

    #if (CPU_FRQ_150MHZ)                       // CPU_FRQ_150MHz is defined in DSP2833x_Examples.h
	/* The following block for all 150 MHz SYSCLKOUT (75 MHz CAN clock) - default. Bit rate = 1 Mbps
	   See Note at end of file */
		ECanbShadow.CANBTC.bit.BRPREG = 4;
		ECanbShadow.CANBTC.bit.TSEG2REG = 2;
		ECanbShadow.CANBTC.bit.TSEG1REG = 10;
	#endif
	#if (CPU_FRQ_100MHZ)                       // CPU_FRQ_100MHz is defined in DSP2833x_Examples.h
	/* The following block is only for 100 MHz SYSCLKOUT (50 MHz CAN clock). Bit rate = 1 Mbps
	   See Note at end of file */
	    ECanbShadow.CANBTC.bit.BRPREG = 4;
		ECanbShadow.CANBTC.bit.TSEG2REG = 1;
		ECanbShadow.CANBTC.bit.TSEG1REG = 6;
	#endif

    ECanbShadow.CANBTC.bit.SAM = 1;
    ECanbRegs.CANBTC.all = ECanbShadow.CANBTC.all;

    ECanbShadow.CANMC.all = ECanbRegs.CANMC.all;
	ECanbShadow.CANMC.bit.CCR = 0 ;            // Set CCR = 0
    ECanbRegs.CANMC.all = ECanbShadow.CANMC.all;

    ECanbShadow.CANES.all = ECanbRegs.CANES.all;

    do
    {
        ECanbShadow.CANES.all = ECanbRegs.CANES.all;
    } while(ECanbShadow.CANES.bit.CCE != 0 ); 		// Wait for CCE bit to be  cleared..


/* Disable all Mailboxes  */
 	ECanbRegs.CANME.all = 0;		// Required before writing the MSGIDs

    EDIS;
}
#endif // if DSP28_ECANB


//---------------------------------------------------------------------------
// Example: InitECanGpio:
//---------------------------------------------------------------------------
// This function initializes GPIO pins to function as eCAN pins
//
// Each GPIO pin can be configured as a GPIO pin or up to 3 different
// peripheral functional pins. By default all pins come up as GPIO
// inputs after reset.
//
// Caution:
// Only one GPIO pin should be enabled for CANTXA/B operation.
// Only one GPIO pin shoudl be enabled for CANRXA/B operation.
// Comment out other unwanted lines.


void InitECanGpio(void)
{
   InitECanaGpio();
#if (DSP28_ECANB)
   InitECanbGpio();
#endif // if DSP28_ECANB
}

void InitECanaGpio(void)
{
   EALLOW;

/* Enable internal pull-up for the selected CAN pins */
// Pull-ups can be enabled or disabled by the user.
// This will enable the pullups for the specified pins.
// Comment out other unwanted lines.

	//GpioCtrlRegs.GPAPUD.bit.GPIO30 = 0;	    // Enable pull-up for GPIO30 (CANRXA)
	GpioCtrlRegs.GPAPUD.bit.GPIO18 = 0;	    // Enable pull-up for GPIO18 (CANRXA)

	//GpioCtrlRegs.GPAPUD.bit.GPIO31 = 0;	    // Enable pull-up for GPIO31 (CANTXA)
	GpioCtrlRegs.GPAPUD.bit.GPIO19 = 0;	    // Enable pull-up for GPIO19 (CANTXA)

/* Set qualification for selected CAN pins to asynch only */
// Inputs are synchronized to SYSCLKOUT by default.
// This will select asynch (no qualification) for the selected pins.

  // GpioCtrlRegs.GPAQSEL2.bit.GPIO30 = 3;   // Asynch qual for GPIO30 (CANRXA)
 GpioCtrlRegs.GPAQSEL2.bit.GPIO18 = 3;   // Asynch qual for GPIO18 (CANRXA)


/* Configure eCAN-A pins using GPIO regs*/
// This specifies which of the possible GPIO pins will be eCAN functional pins.

//GpioCtrlRegs.GPAMUX2.bit.GPIO30 = 1;	// Configure GPIO30 for CANRXA operation
 GpioCtrlRegs.GPAMUX2.bit.GPIO18 = 3;	// Configure GPIO18 for CANRXA operation
//	GpioCtrlRegs.GPAMUX2.bit.GPIO31 = 1;	// Configure GPIO31 for CANTXA operation
 GpioCtrlRegs.GPAMUX2.bit.GPIO19 = 3;	// Configure GPIO19 for CANTXA operation

    EDIS;
}

#if (DSP28_ECANB)
void InitECanbGpio(void)
{
   EALLOW;

/* Enable internal pull-up for the selected CAN pins */
// Pull-ups can be enabled or disabled by the user.
// This will enable the pullups for the specified pins.
// Comment out other unwanted lines.

	GpioCtrlRegs.GPAPUD.bit.GPIO8 = 0;	  // Enable pull-up for GPIO8  (CANTXB)
//  GpioCtrlRegs.GPAPUD.bit.GPIO12 = 0;   // Enable pull-up for GPIO12 (CANTXB)
//  GpioCtrlRegs.GPAPUD.bit.GPIO16 = 0;   // Enable pull-up for GPIO16 (CANTXB)
//  GpioCtrlRegs.GPAPUD.bit.GPIO20 = 0;   // Enable pull-up for GPIO20 (CANTXB)

	GpioCtrlRegs.GPAPUD.bit.GPIO10 = 0;	  // Enable pull-up for GPIO10 (CANRXB)
//  GpioCtrlRegs.GPAPUD.bit.GPIO13 = 0;   // Enable pull-up for GPIO13 (CANRXB)
//  GpioCtrlRegs.GPAPUD.bit.GPIO17 = 0;   // Enable pull-up for GPIO17 (CANRXB)
//  GpioCtrlRegs.GPAPUD.bit.GPIO21 = 0;   // Enable pull-up for GPIO21 (CANRXB)

/* Set qualification for selected CAN pins to asynch only */
// Inputs are synchronized to SYSCLKOUT by default.
// This will select asynch (no qualification) for the selected pins.
// Comment out other unwanted lines.

    GpioCtrlRegs.GPAQSEL1.bit.GPIO10 = 3; // Asynch qual for GPIO10 (CANRXB)
//  GpioCtrlRegs.GPAQSEL1.bit.GPIO13 = 3; // Asynch qual for GPIO13 (CANRXB)
//  GpioCtrlRegs.GPAQSEL2.bit.GPIO17 = 3; // Asynch qual for GPIO17 (CANRXB)
//  GpioCtrlRegs.GPAQSEL2.bit.GPIO21 = 3; // Asynch qual for GPIO21 (CANRXB)

/* Configure eCAN-B pins using GPIO regs*/
// This specifies which of the possible GPIO pins will be eCAN functional pins.

	GpioCtrlRegs.GPAMUX1.bit.GPIO8 = 2;   // Configure GPIO8 for CANTXB operation
//  GpioCtrlRegs.GPAMUX1.bit.GPIO12 = 2;  // Configure GPIO12 for CANTXB operation
//  GpioCtrlRegs.GPAMUX2.bit.GPIO16 = 2;  // Configure GPIO16 for CANTXB operation
//  GpioCtrlRegs.GPAMUX2.bit.GPIO20 = 3;  // Configure GPIO20 for CANTXB operation

	GpioCtrlRegs.GPAMUX1.bit.GPIO10 = 2;  // Configure GPIO10 for CANRXB operation
//  GpioCtrlRegs.GPAMUX1.bit.GPIO13 = 2;  // Configure GPIO13 for CANRXB operation
//  GpioCtrlRegs.GPAMUX2.bit.GPIO17 = 2;  // Configure GPIO17 for CANRXB operation
//  GpioCtrlRegs.GPAMUX2.bit.GPIO21 = 3;  // Configure GPIO21 for CANRXB operation

    EDIS;
}
#endif // if DSP28_ECANB

/*
Note: Bit timing parameters must be chosen based on the network parameters such
as the sampling point desired and the propagation delay of the network.
The propagation delay is a function of length of the cable, delay introduced by
the transceivers and opto/galvanic-isolators (if any).

The parameters used in this file must be changed taking into account the above
mentioned factors in order to arrive at the bit-timing parameters suitable
for a network.

*/

3. CAn rx

Fullscreen 7041.rx_can125_mbox2.txt Download

// TI File $Revision: /main/2 $
// Checkin $Date: July 30, 2009   18:44:22 $
//###########################################################################
// Filename: Example_28xEcan_A_to_B_Xmit.c
//
// Description: eCANA-1 to eCANA2 Transmit loop
//
// ASSUMPTIONS:
//
//    This program requires the DSP2833x header files.
//
//    The CAN ports A of the two 2833x DSP need to be connected
//    to each other (via CAN transceivers)0



//
//      Transmitter end- eCANA1 is on GPIO19 (CANTXA)  and
//                   GPIO18 (CANRXA)
//
//    Reciever end-  eCANA2 is on GPIO19  (CANTXB)  and
//                   GPIO18 (CANRXB)
//
//    As supplied, this project is configured for "boot to SARAM"
//    operation.  The 2833x Boot Mode table is shown below.
//    For information on configuring the boot mode of an eZdsp,
//    please refer to the documentation included with the eZdsp,
//
//       $Boot_Table:
//
//         GPIO87   GPIO86     GPIO85   GPIO84
//          XA15     XA14       XA13     XA12
//           PU       PU         PU       PU
//        ==========================================
//            1        1          1        1    Jump to Flash
//            1        1          1        0    SCI-A boot
//            1        1          0        1    SPI-A boot
//            1        1          0        0    I2C-A boot
//            1        0          1        1    eCAN-A boot
//            1        0          1        0    McBSP-A boot
//            1        0          0        1    Jump to XINTF x16
//            1        0          0        0    Jump to XINTF x32
//            0        1          1        1    Jump to OTP
//            0        1          1        0    Parallel GPIO I/O boot
//            0        1          0        1    Parallel XINTF boot
//            0        1          0        0    Jump to SARAM       <- "boot to SARAM"
//            0        0          1        1    Branch to check boot mode
//            0        0          1        0    Boot to flash, bypass ADC cal
//            0        0          0        1    Boot to SARAM, bypass ADC cal
//            0        0          0        0    Boot to SCI-A, bypass ADC cal
//                                              Boot_Table_End$
//
// DESCRIPTION:
//
//    This example TRANSMITS data from MAILBOX5, CANA on DSP1 to another DS2P CANA module MAILBOX1
//    This program could either loop forever or transmit "n" # of times,
//    where "n" is the TXCOUNT value.
//
// ###########################################################################

#include "DSP28x_Project.h"

// Prototype statements for functions found within this file.

// Global Variables

/* Create a shadow register structure for the CAN control registers. This is
 needed, since, only 32-bit access is allowed to these registers. 16-bit access
 to these registers could potentially corrupt the register contents. This is
 especially true while writing to a bit (or group of bits) among bits 16 - 31 */

struct  ECAN_REGS ECanaShadow;

main()
{
// Initialize System Control registers, PLL, WatchDog, Clocks to default state:
// This function is found in the DSP28_SysCtrl.c file.
    InitSysCtrl();

// Initialise the physical pins of the DSP
    //* Initialize the CAN module */

    InitECan();

/* Write to the MSGID field - MBX number is written as its MSGID */
    ECanaMboxes.MBOX2.MSGID.all  = 0x00050000;  // extended identifier
    ECanaMboxes.MBOX2.MSGID.bit.IDE = 0;

/* Configure Mailbox 1 as Receiver mailbox */
    ECanaShadow.CANMD.all = ECanaRegs.CANMD.all;
    ECanaShadow.CANMD.bit.MD2 = 1;
    ECanaRegs.CANMD.all = ECanaShadow.CANMD.all;
    ECanaMboxes.MBOX2.MSGCTRL.all  = 0;

    ECanaMboxes.MBOX2.MSGCTRL.bit.DLC = 8;
/* Enable Mailbox 1  */

    ECanaShadow.CANME.all = ECanaRegs.CANME.all;
    ECanaShadow.CANME.bit.ME2 = 1;
    ECanaRegs.CANME.all = ECanaShadow.CANME.all;

/* Begin Receiving */
   while(1)
    {
     do {
        ECanaShadow.CANRMP.all = ECanaRegs.CANRMP.all;
        }
        while(ECanaShadow.CANRMP.bit.RMP1 != 1 );       // Wait for RMP1 to be set..

     ECanaShadow.CANRMP.bit.RMP1 = 1;
     ECanaRegs.CANRMP.all = ECanaShadow.CANRMP.all;    // Clear RMP1 bit and start again



    }

}

4. can rx.c

Fullscreen 1665.rx_intialisation.txt Download

// TI File $Revision: /main/8 $
// Checkin $Date: June 25, 2008   15:19:07 $
//###########################################################################
//
// FILE:	DSP2833x_ECan.c
//
// TITLE:	DSP2833x Enhanced CAN Initialization & Support Functions.
//
//###########################################################################
// $TI Release: 2833x/2823x Header Files V1.32 $
// $Release Date: June 28, 2010 $
//###########################################################################

#include "DSP2833x_Device.h"     // DSP2833x Headerfile Include File
#include "DSP2833x_Examples.h"   // DSP2833x Examples Include File


//---------------------------------------------------------------------------
// InitECan:
//---------------------------------------------------------------------------
// This function initializes the eCAN module to a known state.
//
void InitECan(void)
{
   InitECana();
#if DSP28_ECANB
   InitECanb();
#endif // if DSP28_ECANB
}

void InitECana(void)		// Initialize eCAN-A module
{
/* Create a shadow register structure for the CAN control registers. This is
 needed, since only 32-bit access is allowed to these registers. 16-bit access
 to these registers could potentially corrupt the register contents or return
 false data. This is especially true while writing to/reading from a bit
 (or group of bits) among bits 16 - 31 */

struct ECAN_REGS ECanaShadow;

	EALLOW;		// EALLOW enables access to protected bits

/* Configure eCAN RX and TX pins for CAN operation using eCAN regs*/

    ECanaShadow.CANTIOC.all = ECanaRegs.CANTIOC.all;
    ECanaShadow.CANTIOC.bit.TXFUNC = 1;
    ECanaRegs.CANTIOC.all = ECanaShadow.CANTIOC.all;

    ECanaShadow.CANRIOC.all = ECanaRegs.CANRIOC.all;
    ECanaShadow.CANRIOC.bit.RXFUNC = 1;
    ECanaRegs.CANRIOC.all = ECanaShadow.CANRIOC.all;

/* Configure eCAN for SCC mode - (reqd to access mailboxes 0 to 15) */


	ECanaShadow.CANMC.all = ECanaRegs.CANMC.all;
	ECanaShadow.CANMC.bit.SCB = 0;
	ECanaRegs.CANMC.all = ECanaShadow.CANMC.all;

/* Initialize all bits of 'Master Control Field' to zero */
// Some bits of MSGCTRL register come up in an unknown state. For proper operation,
// all bits (including reserved bits) of MSGCTRL must be initialized to zero

    //ECanaMboxes.MBOX0.MSGCTRL.all = 0x00000000;
    //ECanaMboxes.MBOX1.MSGCTRL.all = 0x00000000;
   ECanaMboxes.MBOX2.MSGCTRL.all = 0x00000000;
   // ECanaMboxes.MBOX3.MSGCTRL.all = 0x00000000;
    //ECanaMboxes.MBOX4.MSGCTRL.all = 0x00000000;
   // ECanaMboxes.MBOX5.MSGCTRL.all = 0x00000000;
    //ECanaMboxes.MBOX6.MSGCTRL.all = 0x00000000;
    //ECanaMboxes.MBOX7.MSGCTRL.all = 0x00000000;
   // ECanaMboxes.MBOX8.MSGCTRL.all = 0x00000000;
   // ECanaMboxes.MBOX9.MSGCTRL.all = 0x00000000;
   // ECanaMboxes.MBOX10.MSGCTRL.all = 0x00000000;
   // ECanaMboxes.MBOX11.MSGCTRL.all = 0x00000000;
   // ECanaMboxes.MBOX12.MSGCTRL.all = 0x00000000;
   // ECanaMboxes.MBOX13.MSGCTRL.all = 0x00000000;
   // ECanaMboxes.MBOX14.MSGCTRL.all = 0x00000000;
   // ECanaMboxes.MBOX15.MSGCTRL.all = 0x00000000;
    //ECanaMboxes.MBOX16.MSGCTRL.all = 0x00000000;
    //ECanaMboxes.MBOX17.MSGCTRL.all = 0x00000000;
 //   ECanaMboxes.MBOX18.MSGCTRL.all = 0x00000000;
    //ECanaMboxes.MBOX19.MSGCTRL.all = 0x00000000;
   // ECanaMboxes.MBOX20.MSGCTRL.all = 0x00000000;
   // ECanaMboxes.MBOX21.MSGCTRL.all = 0x00000000;
   // ECanaMboxes.MBOX22.MSGCTRL.all = 0x00000000;
 //   ECanaMboxes.MBOX23.MSGCTRL.all = 0x00000000;
  //  ECanaMboxes.MBOX24.MSGCTRL.all = 0x00000000;
  //  ECanaMboxes.MBOX25.MSGCTRL.all = 0x00000000;
   // ECanaMboxes.MBOX26.MSGCTRL.all = 0x00000000;
   // ECanaMboxes.MBOX27.MSGCTRL.all = 0x00000000;
   // ECanaMboxes.MBOX28.MSGCTRL.all = 0x00000000;
   // ECanaMboxes.MBOX29.MSGCTRL.all = 0x00000000;
   // ECanaMboxes.MBOX30.MSGCTRL.all = 0x00000000;
   // ECanaMboxes.MBOX31.MSGCTRL.all = 0x00000000;

// TAn, RMPn, GIFn bits are all zero upon reset and are cleared again
//	as a matter of precaution.

	//ECanaRegs.CANTA.bit.TA1 = 1 ;	/* Clear all TA1 bits */

	ECanaRegs.CANRMP.bit.RMP1 = 1;	/* Clear all RMPn bits */

	ECanaRegs.CANGIF0.all = 0xFFFFFFFF;	/* Clear all interrupt flag bits */
	ECanaRegs.CANGIF1.all = 0xFFFFFFFF;


/* Configure bit timing parameters for eCANA*/
	ECanaShadow.CANMC.all = ECanaRegs.CANMC.all;
	ECanaShadow.CANMC.bit.CCR = 1 ;            // Set CCR = 1
    ECanaRegs.CANMC.all = ECanaShadow.CANMC.all;

    ECanaShadow.CANES.all = ECanaRegs.CANES.all;

    do
	{
	    ECanaShadow.CANES.all = ECanaRegs.CANES.all;
    } while(ECanaShadow.CANES.bit.CCE != 1 );  		// Wait for CCE bit to be set..

    ECanaShadow.CANBTC.all = 0;

    #if (CPU_FRQ_150MHZ)                       // CPU_FRQ_150MHz is defined in DSP2833x_Examples.h
		/* The following block for all 150 MHz SYSCLKOUT (75 MHz CAN clock) - default. Bit rate = 1 Mbps
		   See Note at End of File */
			ECanaShadow.CANBTC.bit.BRPREG = 39;
			ECanaShadow.CANBTC.bit.TSEG2REG = 2;
			ECanaShadow.CANBTC.bit.TSEG1REG = 10;
    #endif
	#if (CPU_FRQ_100MHZ)                       // CPU_FRQ_100MHz is defined in DSP2833x_Examples.h
	/* The following block is only for 100 MHz SYSCLKOUT (50 MHz CAN clock). Bit rate = 1 Mbps
	   See Note at End of File */
	    ECanaShadow.CANBTC.bit.BRPREG = 4;
		ECanaShadow.CANBTC.bit.TSEG2REG = 1;
		ECanaShadow.CANBTC.bit.TSEG1REG = 6;
	#endif


    ECanaShadow.CANBTC.bit.SAM = 1;
    ECanaRegs.CANBTC.all = ECanaShadow.CANBTC.all;

    ECanaShadow.CANMC.all = ECanaRegs.CANMC.all;
	ECanaShadow.CANMC.bit.CCR = 0 ;            // Set CCR = 0
    ECanaRegs.CANMC.all = ECanaShadow.CANMC.all;

    ECanaShadow.CANES.all = ECanaRegs.CANES.all;

    do
    {
       ECanaShadow.CANES.all = ECanaRegs.CANES.all;
    } while(ECanaShadow.CANES.bit.CCE != 0 ); 		// Wait for CCE bit to be  cleared..

/* Disable all Mailboxes  */
 	ECanaRegs.CANME.all = 0;		// Required before writing the MSGIDs

    EDIS;
}


#if (DSP28_ECANB)
void InitECanb(void)		// Initialize eCAN-B module
{
/* Create a shadow register structure for the CAN control registers. This is
 needed, since only 32-bit access is allowed to these registers. 16-bit access
 to these registers could potentially corrupt the register contents or return
 false data. This is especially true while writing to/reading from a bit
 (or group of bits) among bits 16 - 31 */

struct ECAN_REGS ECanbShadow;

   EALLOW;		// EALLOW enables access to protected bits

/* Configure eCAN RX and TX pins for CAN operation using eCAN regs*/

    ECanbShadow.CANTIOC.all = ECanbRegs.CANTIOC.all;
    ECanbShadow.CANTIOC.bit.TXFUNC = 1;
    ECanbRegs.CANTIOC.all = ECanbShadow.CANTIOC.all;

    ECanbShadow.CANRIOC.all = ECanbRegs.CANRIOC.all;
    ECanbShadow.CANRIOC.bit.RXFUNC = 1;
    ECanbRegs.CANRIOC.all = ECanbShadow.CANRIOC.all;

/* Configure eCAN for HECC mode - (reqd to access mailboxes 16 thru 31) */

	ECanbShadow.CANMC.all = ECanbRegs.CANMC.all;
	ECanbShadow.CANMC.bit.SCB = 1;
	ECanbRegs.CANMC.all = ECanbShadow.CANMC.all;

/* Initialize all bits of 'Master Control Field' to zero */
// Some bits of MSGCTRL register come up in an unknown state. For proper operation,
// all bits (including reserved bits) of MSGCTRL must be initialized to zero

    ECanbMboxes.MBOX0.MSGCTRL.all = 0x00000000;
    ECanbMboxes.MBOX1.MSGCTRL.all = 0x00000000;
    ECanbMboxes.MBOX2.MSGCTRL.all = 0x00000000;
    ECanbMboxes.MBOX3.MSGCTRL.all = 0x00000000;
    ECanbMboxes.MBOX4.MSGCTRL.all = 0x00000000;
    ECanbMboxes.MBOX5.MSGCTRL.all = 0x00000000;
    ECanbMboxes.MBOX6.MSGCTRL.all = 0x00000000;
    ECanbMboxes.MBOX7.MSGCTRL.all = 0x00000000;
    ECanbMboxes.MBOX8.MSGCTRL.all = 0x00000000;
    ECanbMboxes.MBOX9.MSGCTRL.all = 0x00000000;
    ECanbMboxes.MBOX10.MSGCTRL.all = 0x00000000;
    ECanbMboxes.MBOX11.MSGCTRL.all = 0x00000000;
    ECanbMboxes.MBOX12.MSGCTRL.all = 0x00000000;
    ECanbMboxes.MBOX13.MSGCTRL.all = 0x00000000;
    ECanbMboxes.MBOX14.MSGCTRL.all = 0x00000000;
    ECanbMboxes.MBOX15.MSGCTRL.all = 0x00000000;
    ECanbMboxes.MBOX16.MSGCTRL.all = 0x00000000;
    ECanbMboxes.MBOX17.MSGCTRL.all = 0x00000000;
    ECanbMboxes.MBOX18.MSGCTRL.all = 0x00000000;
    ECanbMboxes.MBOX19.MSGCTRL.all = 0x00000000;
    ECanbMboxes.MBOX20.MSGCTRL.all = 0x00000000;
    ECanbMboxes.MBOX21.MSGCTRL.all = 0x00000000;
    ECanbMboxes.MBOX22.MSGCTRL.all = 0x00000000;
    ECanbMboxes.MBOX23.MSGCTRL.all = 0x00000000;
    ECanbMboxes.MBOX24.MSGCTRL.all = 0x00000000;
    ECanbMboxes.MBOX25.MSGCTRL.all = 0x00000000;
    ECanbMboxes.MBOX26.MSGCTRL.all = 0x00000000;
    ECanbMboxes.MBOX27.MSGCTRL.all = 0x00000000;
    ECanbMboxes.MBOX28.MSGCTRL.all = 0x00000000;
    ECanbMboxes.MBOX29.MSGCTRL.all = 0x00000000;
    ECanbMboxes.MBOX30.MSGCTRL.all = 0x00000000;
    ECanbMboxes.MBOX31.MSGCTRL.all = 0x00000000;

// TAn, RMPn, GIFn bits are all zero upon reset and are cleared again
//	as a matter of precaution.

	ECanbRegs.CANTA.all	= 0xFFFFFFFF;	/* Clear all TAn bits */

	ECanbRegs.CANRMP.all = 0xFFFFFFFF;	/* Clear all RMPn bits */

	ECanbRegs.CANGIF0.all = 0xFFFFFFFF;	/* Clear all interrupt flag bits */
	ECanbRegs.CANGIF1.all = 0xFFFFFFFF;


/* Configure bit timing parameters for eCANB*/

	ECanbShadow.CANMC.all = ECanbRegs.CANMC.all;
	ECanbShadow.CANMC.bit.CCR = 1 ;            // Set CCR = 1
    ECanbRegs.CANMC.all = ECanbShadow.CANMC.all;

    ECanbShadow.CANES.all = ECanbRegs.CANES.all;

    do
	{
	    ECanbShadow.CANES.all = ECanbRegs.CANES.all;
	} while(ECanbShadow.CANES.bit.CCE != 1 ); 		// Wait for CCE bit to be  cleared..


    ECanbShadow.CANBTC.all = 0;

    #if (CPU_FRQ_150MHZ)                       // CPU_FRQ_150MHz is defined in DSP2833x_Examples.h
	/* The following block for all 150 MHz SYSCLKOUT (75 MHz CAN clock) - default. Bit rate = 1 Mbps
	   See Note at end of file */
		ECanbShadow.CANBTC.bit.BRPREG = 4;
		ECanbShadow.CANBTC.bit.TSEG2REG = 2;
		ECanbShadow.CANBTC.bit.TSEG1REG = 10;
	#endif
	#if (CPU_FRQ_100MHZ)                       // CPU_FRQ_100MHz is defined in DSP2833x_Examples.h
	/* The following block is only for 100 MHz SYSCLKOUT (50 MHz CAN clock). Bit rate = 1 Mbps
	   See Note at end of file */
	    ECanbShadow.CANBTC.bit.BRPREG = 4;
		ECanbShadow.CANBTC.bit.TSEG2REG = 1;
		ECanbShadow.CANBTC.bit.TSEG1REG = 6;
	#endif

    ECanbShadow.CANBTC.bit.SAM = 1;
    ECanbRegs.CANBTC.all = ECanbShadow.CANBTC.all;

    ECanbShadow.CANMC.all = ECanbRegs.CANMC.all;
	ECanbShadow.CANMC.bit.CCR = 0 ;            // Set CCR = 0
    ECanbRegs.CANMC.all = ECanbShadow.CANMC.all;

    ECanbShadow.CANES.all = ECanbRegs.CANES.all;

    do
    {
        ECanbShadow.CANES.all = ECanbRegs.CANES.all;
    } while(ECanbShadow.CANES.bit.CCE != 0 ); 		// Wait for CCE bit to be  cleared..


/* Disable all Mailboxes  */
 	ECanbRegs.CANME.all = 0;		// Required before writing the MSGIDs

    EDIS;
}
#endif // if DSP28_ECANB


//---------------------------------------------------------------------------
// Example: InitECanGpio:
//---------------------------------------------------------------------------
// This function initializes GPIO pins to function as eCAN pins
//
// Each GPIO pin can be configured as a GPIO pin or up to 3 different
// peripheral functional pins. By default all pins come up as GPIO
// inputs after reset.
//
// Caution:
// Only one GPIO pin should be enabled for CANTXA/B operation.
// Only one GPIO pin shoudl be enabled for CANRXA/B operation.
// Comment out other unwanted lines.


void InitECanGpio(void)
{
   InitECanaGpio();
#if (DSP28_ECANB)
   InitECanbGpio();
#endif // if DSP28_ECANB
}

void InitECanaGpio(void)
{
   EALLOW;

/* Enable internal pull-up for the selected CAN pins */
// Pull-ups can be enabled or disabled by the user.
// This will enable the pullups for the specified pins.
// Comment out other unwanted lines.

	//GpioCtrlRegs.GPAPUD.bit.GPIO30 = 0;	    // Enable pull-up for GPIO30 (CANRXA)
	GpioCtrlRegs.GPAPUD.bit.GPIO18 = 0;	    // Enable pull-up for GPIO18 (CANRXA)

	//GpioCtrlRegs.GPAPUD.bit.GPIO31 = 0;	    // Enable pull-up for GPIO31 (CANTXA)
	GpioCtrlRegs.GPAPUD.bit.GPIO19 = 0;	    // Enable pull-up for GPIO19 (CANTXA)

/* Set qualification for selected CAN pins to asynch only */
// Inputs are synchronized to SYSCLKOUT by default.
// This will select asynch (no qualification) for the selected pins.

  // GpioCtrlRegs.GPAQSEL2.bit.GPIO30 = 3;   // Asynch qual for GPIO30 (CANRXA)
 GpioCtrlRegs.GPAQSEL2.bit.GPIO18 = 3;   // Asynch qual for GPIO18 (CANRXA)


/* Configure eCAN-A pins using GPIO regs*/
// This specifies which of the possible GPIO pins will be eCAN functional pins.

//GpioCtrlRegs.GPAMUX2.bit.GPIO30 = 1;	// Configure GPIO30 for CANRXA operation
 GpioCtrlRegs.GPAMUX2.bit.GPIO18 = 3;	// Configure GPIO18 for CANRXA operation
//	GpioCtrlRegs.GPAMUX2.bit.GPIO31 = 1;	// Configure GPIO31 for CANTXA operation
 GpioCtrlRegs.GPAMUX2.bit.GPIO19 = 3;	// Configure GPIO19 for CANTXA operation

    EDIS;
}

#if (DSP28_ECANB)
void InitECanbGpio(void)
{
   EALLOW;

/* Enable internal pull-up for the selected CAN pins */
// Pull-ups can be enabled or disabled by the user.
// This will enable the pullups for the specified pins.
// Comment out other unwanted lines.

	GpioCtrlRegs.GPAPUD.bit.GPIO8 = 0;	  // Enable pull-up for GPIO8  (CANTXB)
//  GpioCtrlRegs.GPAPUD.bit.GPIO12 = 0;   // Enable pull-up for GPIO12 (CANTXB)
//  GpioCtrlRegs.GPAPUD.bit.GPIO16 = 0;   // Enable pull-up for GPIO16 (CANTXB)
//  GpioCtrlRegs.GPAPUD.bit.GPIO20 = 0;   // Enable pull-up for GPIO20 (CANTXB)

	GpioCtrlRegs.GPAPUD.bit.GPIO10 = 0;	  // Enable pull-up for GPIO10 (CANRXB)
//  GpioCtrlRegs.GPAPUD.bit.GPIO13 = 0;   // Enable pull-up for GPIO13 (CANRXB)
//  GpioCtrlRegs.GPAPUD.bit.GPIO17 = 0;   // Enable pull-up for GPIO17 (CANRXB)
//  GpioCtrlRegs.GPAPUD.bit.GPIO21 = 0;   // Enable pull-up for GPIO21 (CANRXB)

/* Set qualification for selected CAN pins to asynch only */
// Inputs are synchronized to SYSCLKOUT by default.
// This will select asynch (no qualification) for the selected pins.
// Comment out other unwanted lines.

    GpioCtrlRegs.GPAQSEL1.bit.GPIO10 = 3; // Asynch qual for GPIO10 (CANRXB)
//  GpioCtrlRegs.GPAQSEL1.bit.GPIO13 = 3; // Asynch qual for GPIO13 (CANRXB)
//  GpioCtrlRegs.GPAQSEL2.bit.GPIO17 = 3; // Asynch qual for GPIO17 (CANRXB)
//  GpioCtrlRegs.GPAQSEL2.bit.GPIO21 = 3; // Asynch qual for GPIO21 (CANRXB)

/* Configure eCAN-B pins using GPIO regs*/
// This specifies which of the possible GPIO pins will be eCAN functional pins.

	GpioCtrlRegs.GPAMUX1.bit.GPIO8 = 2;   // Configure GPIO8 for CANTXB operation
//  GpioCtrlRegs.GPAMUX1.bit.GPIO12 = 2;  // Configure GPIO12 for CANTXB operation
//  GpioCtrlRegs.GPAMUX2.bit.GPIO16 = 2;  // Configure GPIO16 for CANTXB operation
//  GpioCtrlRegs.GPAMUX2.bit.GPIO20 = 3;  // Configure GPIO20 for CANTXB operation

	GpioCtrlRegs.GPAMUX1.bit.GPIO10 = 2;  // Configure GPIO10 for CANRXB operation
//  GpioCtrlRegs.GPAMUX1.bit.GPIO13 = 2;  // Configure GPIO13 for CANRXB operation
//  GpioCtrlRegs.GPAMUX2.bit.GPIO17 = 2;  // Configure GPIO17 for CANRXB operation
//  GpioCtrlRegs.GPAMUX2.bit.GPIO21 = 3;  // Configure GPIO21 for CANRXB operation

    EDIS;
}
#endif // if DSP28_ECANB

/*
Note: Bit timing parameters must be chosen based on the network parameters such
as the sampling point desired and the propagation delay of the network.
The propagation delay is a function of length of the cable, delay introduced by
the transceivers and opto/galvanic-isolators (if any).

The parameters used in this file must be changed taking into account the above
mentioned factors in order to arrive at the bit-timing parameters suitable
for a network.

*/

hope you can help.

regards

Sneha

0 Sneha Thakur over 10 years ago in reply to Sneha Thakur

Expert 2660 points

Hi Adam

Please help me sort out the issue as I am not able to resolve the same.

Thanks & Regards

Sneha

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