• State Resolved
  • Locked Locked
  • Replies 2 replies
  • Subscribers 82 subscribers
  • Views 1030 views
  • Users 0 members are here
Support feedback
Options
Options
Related

This thread has been locked.

If you have a related question, please click the "Ask a related question" button in the top right corner. The newly created question will be automatically linked to this question.

EMIF in 28377d

Abhijit Kelkar
Intellectual 855 points

Dear All,

We will be using EMIF in 28377D to interface with external FPGA. The FPGA contains some hard-coded logic & will require clock for execution of logic. Similarly we need to transfer some 32 bit data variables to carry out that logic. We will be using EMIF in SRAM configuration. If I configure EMIF in Asynchronous memory interface mode then

1. Can  I get  EM1CLK  on GPIO pin if I make necessary multiplexing on particular GPIO?

2. Will that EM1CLK will be available on continuous basic irrespective of my memory interface commands 

I am asking this question as technical manual mentions that EM1CLK signal is to be used for SDRAM configuration .

Thanks in advance & regards

Abhijit 

  • 0
    TI__Guru** 116581 points

    Hi Abhijit,

    1. Can  I get  EM1CLK  on GPIO pin if I make necessary multiplexing on particular GPIO?

    Yes, EM1CLK will be available but the max frq at which this output buffer can toggle is 100MHz where as max frq supported for SRAM is 200MHz. To get the reliable clock, you need to operate EMIF at 100MHz. Other important point is that in ASYNC mode clock is not used (used in SDRAM mode only) hence no timing information is available between EM1CLK and other signals of SRAM interface.

    2. Will that EM1CLK will be available on continuous basic irrespective of my memory interface commands 

    Yes, it'll be continious clock.

    Regards,

    Vivek Singh

     

  • 0 in reply to Vivek Singh
    Intellectual 855 points

    Thanks Vivek,

    1. Great. I will be using EM1CLK for some FPGA Hard logic. In 28377D technical manual ASYNC read/Write diagrams are given w.r.t. EM1CLK but in description of EMIF signals EM1CLK was referred for SDRAM only so I wanted to confirm.

    2.Good.

    regards

    Abhijit Kelkar