TMS320f28069 CLA: CLA is not working as expected after power-cycle

Further Information:

The CLA program counter (MPC) is 0x0070 - this is the start of CLATask1.  During normal operation this is reading out as 0x03BA - this is the end of CLATask1.

This suggests to me that the CLA task never ran at all - but this doesn't explain why the "task complete" interrupt was fired.

Hi,

Does this happen on every power cycle or only when its a WDT reset? How are you triggering task 1?

Vishal_Coelho said:

Hi,

Does this happen on every power cycle or only when its a WDT reset? How are you triggering task 1?

This happens on every power cycle, but so does the WDT reset (i.e. the power supply is turned off and back on, the code always starts up with a WDT reset flagged) - the WDT reset does not occur while debugging and restarting/reprogramming.  Could the WDT reset be linked to the CLA failure?  I will try forcing a WDT reset while debugging and see if the CLA operates when this occurs.

I am triggered task 1 with:

Cla1ForceTask1()

which is #defined as:

__asm("  IACK  #0x0001")

Hmm, sounds like the CLA gets configured, but when it hits the first line of CLA code @ 0x70 it runs into an illegal opcode. If you look at the CLA chapter in the device TRM you will see a section similar to this (I pulled this from the 2837x TRM)

5.3.4 CLA Illegal Opcode Behavior
If the CLA fetches an opcode that does not correspond to a legal instruction, it will behave as follows:
• The CLA will halt with the illegal opcode in the D2 phase of the pipeline as if it were a breakpoint. This
will occur whether CLA breakpoints are enabled or not.
• The CLA will issue the task-specific interrupt to the PIE.
• The MIRUN bit for the task will remain set.
Further single-stepping is ignored once execution halts due to an illegal op-code. To exit this situation,
issue either a soft or hard reset of the CLA as described in Section 5.3.5.

And this is exactly the behavior you described. Every time you hit a reset, whether its a manual power cycle or watchdog reset, you have to assume the CLA is in its reset state i.e. you will need to memcpy() CLA code from flash to ram and then start the CLA initialization process.

Hi Vishal,

Thank you for your reply - this certainly does explain what I am experiencing.

First up, I have just tried triggering a WDT reset while debugging - after the reset, the code operates as per usual (everything working fine).  This suggests to me that the two problems are unrelated.

My initialization procedure is as follows:

- Check if WDT caused reset

- Configure flash  (Copy critical code to flash, calls InitFlash() which is part of F2806x_SysCtrl.c

- InitSysCtrl() (F2806x_SysCtrl.c)

- InitPieCtrl() (F2806x_SysCtrl.c)

- Disable CPU interrupts, clear all flags

- InitPieVectTable() (F2806x_SysCtrl.c)

- init_cla() [Code below]

- Enable wdt

- Enable/init peripherals (CLA1 complete interrupt is enabled here)

- Interrupts enabled

void init_cla(void)
{
	/*  Assign user defined ISR to the PIE vector table */
	EALLOW;
	PieVectTable.CLA1_INT1 = &cla1_task1_isr;
	PieVectTable.CLA1_INT2 = &cla1_task2_isr;
	PieVectTable.CLA1_INT3 = &cla1_task3_isr;
	PieVectTable.CLA1_INT4 = &cla1_task4_isr;
	PieVectTable.CLA1_INT5 = &cla1_task5_isr;
	PieVectTable.CLA1_INT6 = &cla1_task6_isr;
	PieVectTable.CLA1_INT7 = &cla1_task7_isr;
	PieVectTable.CLA1_INT8 = &cla1_task8_isr;
	EDIS;

	//Copy over the CLA code
	memcpy(&Cla1funcsRunStart, &Cla1funcsLoadStart, &Cla1funcsLoadEnd - &Cla1funcsLoadStart);

	// Copy over CLA math tables (Only needed if using CLAMath library
	memcpy(&Cla1mathTablesRunStart, &Cla1mathTablesLoadStart, (Uint32) &Cla1mathTablesLoadSize);

	/*  Compute all CLA task vectors */
	EALLOW;
	Cla1Regs.MVECT1 = ((Uint16) Cla1Task1 - (Uint16) &Cla1Prog_Start);
	Cla1Regs.MVECT2 = ((Uint16) Cla1Task2 - (Uint16) &Cla1Prog_Start);
	Cla1Regs.MVECT3 = ((Uint16) Cla1Task3 - (Uint16) &Cla1Prog_Start);
	Cla1Regs.MVECT4 = ((Uint16) Cla1Task4 - (Uint16) &Cla1Prog_Start);
	Cla1Regs.MVECT5 = ((Uint16) Cla1Task5 - (Uint16) &Cla1Prog_Start);
	Cla1Regs.MVECT6 = ((Uint16) Cla1Task6 - (Uint16) &Cla1Prog_Start);
	Cla1Regs.MVECT7 = ((Uint16) Cla1Task7 - (Uint16) &Cla1Prog_Start);
	Cla1Regs.MVECT8 = ((Uint16) Cla1Task8 - (Uint16) &Cla1Prog_Start);
	EDIS;

	//  Step 3 : Mapping CLA tasks
	/*  All tasks are enabled and will be started by an ePWM trigger
	 *  Map CLA program memory to the CLA and enable software breakpoints
	 */
	EALLOW;
	Cla1Regs.MPISRCSEL1.bit.PERINT1SEL = CLA_INT1_NONE;
	Cla1Regs.MPISRCSEL1.bit.PERINT2SEL = CLA_INT2_NONE;
	Cla1Regs.MPISRCSEL1.bit.PERINT3SEL = CLA_INT3_NONE;
	Cla1Regs.MPISRCSEL1.bit.PERINT4SEL = CLA_INT4_NONE;
	Cla1Regs.MPISRCSEL1.bit.PERINT5SEL = CLA_INT5_NONE;
	Cla1Regs.MPISRCSEL1.bit.PERINT6SEL = CLA_INT6_NONE;
	Cla1Regs.MPISRCSEL1.bit.PERINT7SEL = CLA_INT7_NONE;
	Cla1Regs.MPISRCSEL1.bit.PERINT8SEL = CLA_INT8_NONE;
	Cla1Regs.MIER.all = 0x00FF;
	EDIS;

	/*  Enable CLA interrupts at the group and subgroup levels */
	PieCtrlRegs.PIEIER11.all = 0xFFFF;
	IER |= (M_INT11);
	EINT;
	// Enable Global interrupt INTM
	ERTM;
	// Enable Global realtime interrupt DBGM

	/* Switch the CLA program space to the CLA and enable software forcing
	 * Also switch over CLA data ram 0 and 1
	 */
	EALLOW;
	Cla1Regs.MMEMCFG.bit.PROGE = 1;
	Cla1Regs.MMEMCFG.bit.RAM1CPUE = 1;
	Cla1Regs.MCTL.bit.IACKE = 1;	// Enable the CPU to use IACK to set MIFR bits.
	Cla1Regs.MMEMCFG.bit.RAM0E = CLARAM0_ENABLE;
	Cla1Regs.MMEMCFG.bit.RAM1E = CLARAM1_ENABLE;
	Cla1Regs.MMEMCFG.bit.RAM2E = CLARAM2_ENABLE;
	EDIS;
}

It looks to me like I am correctly copying the CLA functions to RAM.  My linker script is shown below:

_Cla1Prog_Start = _Cla1funcsRunStart;

-heap 0x400
-stack 0x400

// Define a size for the CLA scratchpad area that will be used
// by the CLA compiler for local symbols and temps
// Also force references to the special symbols that mark the
// scratchpad are.
 CLA_SCRATCHPAD_SIZE = 0x100;
--undef_sym=__cla_scratchpad_end
--undef_sym=__cla_scratchpad_start

MEMORY
{
PAGE 0 :
           /* Memory (RAM/FLASH/OTP) blocks can be moved to PAGE1 for data allocation */
   OTP         : origin = 0x3D7800, length = 0x000400     /* on-chip OTP */

   RAML3		: origin = 0x009000, length = 0x001000		/*CLA program RAM*/
   RAML45       : origin = 0x00A000, length = 0x004000     /* on-chip RAM block L4 & L5*/

// Bits of memory used by the bootloader
   VALIDREGION   : origin = 0x3DC000, length = 0x000001     /* on-chip FLASH */	// Stores the "App Valid" value
   APPVERSION    : origin = 0x3DC001, length = 0x000001     /* on-chip FLASH */	// Stores the "App Version" value
   RESERVED0     : origin = 0x3DC002, length = 0x000001     /* on-chip FLASH */	// Section reserved for future use (used by bootloader)
   RESERVED1     : origin = 0x3DC003, length = 0x000001     /* on-chip FLASH */	// Section reserved for future use (used by bootloader)
   RESERVED2     : origin = 0x3DC004, length = 0x000001     /* on-chip FLASH */	// Section reserved for future use (used by bootloader)
   //BEGIN         : origin = 0x3DC005, length = 0x000002     /* Part of FLASHG.  Used for "boot to Flash" bootloader mode. */


   FLASHD      : origin = 0x3E8000, length = 0x004000     /* on-chip FLASH */
   FLASHC      : origin = 0x3EC000, length = 0x004000     /* on-chip FLASH */
   FLASHA      : origin = 0x3F4000, length = 0x003F80     /* on-chip FLASH */
   CSM_RSVD    : origin = 0x3F7F80, length = 0x000076     /* Part of FLASHA.  Program with all 0x0000 when CSM is in use. */
   BEGIN       : origin = 0x3F7FF6, length = 0x000002     /* Part of FLASHA.  Used for "boot to Flash" bootloader mode. */
   CSM_PWL_P0  : origin = 0x3F7FF8, length = 0x000008     /* Part of FLASHA.  CSM password locations in FLASHA */

   FPUTABLES   : origin = 0x3FD860, length = 0x0006A0	  /* FPU Tables in Boot ROM */
   IQTABLES    : origin = 0x3FDF00, length = 0x000B50     /* IQ Math Tables in Boot ROM */
   IQTABLES2   : origin = 0x3FEA50, length = 0x00008C     /* IQ Math Tables in Boot ROM */
   IQTABLES3   : origin = 0x3FEADC, length = 0x0000AA	  /* IQ Math Tables in Boot ROM */

   ROM         : origin = 0x3FF3B0, length = 0x000C10     /* Boot ROM */
   RESET       : origin = 0x3FFFC0, length = 0x000002     /* part of boot ROM  */
   VECTORS     : origin = 0x3FFFC2, length = 0x00003E     /* part of boot ROM  */

PAGE 1 :   /* Data Memory */
           /* Memory (RAM/FLASH/OTP) blocks can be moved to PAGE0 for program allocation */
           /* Registers remain on PAGE1                                                  */

   BOOT_RSVD   : origin = 0x000000, length = 0x000050     /* Part of M0, BOOT rom will use this for stack */
   RAMM0       : origin = 0x000050, length = 0x0003B0     /* on-chip RAM block M0 */
   RAMM1       : origin = 0x000400, length = 0x000400     /* on-chip RAM block M1 */

   CLARAM0              : origin = 0x008800, length = 0x000400		/*L1 DSPSARAM*/
   CLARAM1              : origin = 0x008C00, length = 0x000400		/*L2 DSPSARAM*/
   CLARAM2				: origin = 0x008000, length = 0x000800		/*L0 DSPSARAM*/

   RAML678		: origin = 0x00E000,	length = 0x006000		/* on-chip RAM block L6, L7, L8 */

   /*RAML2       : origin = 0x008C00, length = 0x000400     *//* on-chip RAM block L2 */
   /*RAML3       : origin = 0x009000, length = 0x001000	    *//* on-chip RAM block L3 */
   /*RAML4       : origin = 0x00A000, length = 0x002000     *//* on-chip RAM block L4 */
   /*RAML5       : origin = 0x00C000, length = 0x002000     *//* on-chip RAM block L5 */
   /*RAML6       : origin = 0x00E000, length = 0x002000     *//* on-chip RAM block L6 */
   /*RAML7       : origin = 0x010000, length = 0x002000     *//* on-chip RAM block L7 */
   /*RAML8       : origin = 0x012000, length = 0x002000     *//* on-chip RAM block L8 */

// Sector H is reserved for the bootloader
//   FLASHH      : origin = 0x3D8000, length = 0x004000     /* on-chip FLASH */


// Sector G starts at 7 (after the regions defined in PAGE 0 for the bootloader)
   FLASHG      : origin = 0x3DC007, length = 0x003FF9     /* on-chip FLASH */
   FLASHF      : origin = 0x3E0000, length = 0x004000     /* on-chip FLASH */
   FLASHE      : origin = 0x3E4000, length = 0x004000     /* on-chip FLASH */
   FLASHB      : origin = 0x3F0000, length = 0x004000     /* on-chip FLASH */

   CLA1_MSGRAMLOW       : origin = 0x001480, length = 0x000080
   CLA1_MSGRAMHIGH      : origin = 0x001500, length = 0x000080

}

/* Allocate sections to memory blocks.
   Note:
         codestart user defined section in DSP28_CodeStartBranch.asm used to redirect code
                   execution when booting to flash
         ramfuncs  user defined section to store functions that will be copied from Flash into RAM
*/


SECTIONS
{

   /* Allocate program areas: */
   .cinit              : > FLASHA PAGE = 0
   .pinit              : > FLASHA,     PAGE = 0
   .text               : > FLASHA      PAGE = 0
   codestart           : > BEGIN       PAGE = 0
   ramfuncs            : LOAD = FLASHD,
                         RUN = RAML45,
                         LOAD_START(_RamfuncsLoadStart),
                         LOAD_END(_RamfuncsLoadEnd),
                         RUN_START(_RamfuncsRunStart),
                         PAGE = 0

   csmpasswds          : > CSM_PWL_P0  PAGE = 0
   csm_rsvd            : > CSM_RSVD    PAGE = 0

   /* Allocate uninitalized data sections: */
   .stack              : > RAMM1       PAGE = 1
   .ebss               : > RAML678       PAGE = 1
   .esysmem            : > RAML678       PAGE = 1

   /* Initalized sections to go in Flash */
   /* For SDFlash to program these, they must be allocated to page 0 */
   .econst             : > FLASHA      PAGE = 0
   .switch             : > FLASHA      PAGE = 0

   /* Allocate IQ math areas: */
   IQmath              : > FLASHA      PAGE = 0            /* Math Code */
   IQmathTables        : > IQTABLES,   PAGE = 0, TYPE = NOLOAD

   DMARAML5            : > RAML678,      PAGE = 1
   DMARAML6            : > RAML678,      PAGE = 1
   DMARAML7            : > RAML678,      PAGE = 1
   DMARAML8            : > RAML678,      PAGE = 1

/*** Filter sections ***/
   firldb   align(0x100)> RAML678	 PAGE = 1
   firRiRx  align(0x100)> RAML678	 PAGE = 1
   firCalRx   align(0x100)> RAML678	 PAGE = 1
   firCal   align(0x100)> RAML678	 PAGE = 1
   firModFd  align(0x100)> RAML678	 PAGE = 1 /**/
   firModDemod align(0x100)> RAML678	 PAGE = 1
   firModRx    align(0x100)> RAML678	 PAGE = 1
   firModTx    align(0x100)> RAML678	 PAGE = 1
   firfilt	: >	RAML678	 PAGE = 1

/*** strio lib sections ***/
   slowfuncs         : > RAML45,      PAGE = 0

/*** FFT sections ***/
   FFTtf	>	RAML45, 	 PAGE = 0
   DLOG	 	>	RAML45,	 PAGE =	0
   FFTipcb	ALIGN(2048)  : { } >    RAML45 PAGE 0
   FFTmag   >	RAML45	 PAGE 0


   SINTBL : >	FLASHA	 PAGE = 0

   scopeBufs : >	RAML678	 PAGE = 1
   crcTable  : >    RAML678    PAGE = 1
   fsdata    : >    RAML678    PAGE = 1

  Cla1Prog        : > RAML3,
                     LOAD_START(_Cla1funcsLoadStart),
                     LOAD_END(_Cla1funcsLoadEnd),
                     LOAD_SIZE(_Cla1funcsLoadSize),
                     RUN_START(_Cla1funcsRunStart),
                     PAGE = 0

   Cla1ToCpuMsgRAM  : > CLA1_MSGRAMLOW,   PAGE = 1
   CpuToCla1MsgRAM  : > CLA1_MSGRAMHIGH,  PAGE = 1
   Cla1DataRam0		: > CLARAM0,		  PAGE = 1
   Cla1DataRam1		: > CLARAM1,		  PAGE = 1
   Cla1DataRam2		: > CLARAM2,		  PAGE = 1

   CLA1mathTables	: > CLARAM1,
                      LOAD_START(_Cla1mathTablesLoadStart),
                      LOAD_END(_Cla1mathTablesLoadEnd),
                      LOAD_SIZE(_Cla1mathTablesLoadSize),
                      RUN_START(_Cla1mathTablesRunStart),
                      PAGE = 1

   CLAscratch       :
                     { *.obj(CLAscratch)
                     . += CLA_SCRATCHPAD_SIZE;
                     *.obj(CLAscratch_end) } > CLARAM1,
					 PAGE = 1

   .bss_cla		    : > CLARAM1,   PAGE = 1
   .const_cla	    : > CLARAM1,   PAGE = 1

   /* .reset is a standard section used by the compiler.  It contains the */
   /* the address of the start of _c_int00 for C Code.   /*
   /* When using the boot ROM this section and the CPU vector */
   /* table is not needed.  Thus the default type is set here to  */
   /* DSECT  */
   .reset              : > RESET,      PAGE = 0, TYPE = DSECT
   vectors             : > VECTORS     PAGE = 0, TYPE = DSECT

}

Hi Elliott,

For the RAM cases, i.e. with the emulator connected, the emulator can directly load to the RUN location in RAM but when you remove the JTAG and then power cycle is it boots from FLASH (which i will call standalone mode) and then you would actually need to copy CLA code from FLASH to RAM. The symbols are there in the RAM linker command file to remind people that in standalone mode you will need to copy over code from FLASH to RAM.