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F28377D periphe ral ownership switching

Abhijit Kelkar
Intellectual 855 points

Dear All,

In 28377D there are no. of peripheral like SCI, SPI, EMIF etc. 

Most of peripherals can be owned by either CPU1 or CPU2 except USB. In CPU1 program, one can assign owner ship to CPU1 or CPU2. 

My question is, is it possible to switch the owner ship of particular peripheral in between running program. 

For example suppose initially EMIF control is assigned to CPU2 in CPU1 program but in between software, CPU 1 will gain owner ship of EMIF for some time and after certain task it will again handover control to CPU2. This may happen repeatedly at certain time interval.

Please let me know if it is possible.

Warm regards

Abhijit Kelkar 

  • 0
    Guru 192875 points
    Hi Abhi,

    Nice query. Well, you should be able to achieve this by re-configuring the peripherals registers again and again for switching the ownership. Have you already tried this out? I've not tried this personally but do let me know what your observations are.

    Regards,
    Gautam
  • 0 in reply to Gautam Iyer
    TI__Guru** 116971 points
    Hi Abhijit,
    My question is, is it possible to switch the owner ship of particular peripheral in between running program.

    This is not recommended. When we switch the ownership, CLK to peripheral is also switched and it can create glitch on CLK which could corrupt peripheral state.
    For example suppose initially EMIF control is assigned to CPU2 in CPU1 program but in between software, CPU 1 will gain owner ship of EMIF for some time and after certain task it will again handover control to CPU2. This may happen repeatedly at certain time interval.

    Ownership implementation for EMIF1 is different than other peripheral. All the masters can READ the data from external device irrespective of which CPU have ownership of EMIF1 module. CPU subsystem need to have ownership only for write and execution. If user need to change the ownership for EMIF, then it's recommended to use the IPC to communicate between two CPU to make sure there is no outstanding transaction on EMIF.
    Regards,Vivek Singh
  • 0 in reply to Vivek Singh
    Guru 192875 points
    Thanks Vivek for the confirmation.

    Regards,
    Gautam
  • 0 in reply to Vivek Singh
    Intellectual 855 points
    Thanks Vivek,
    I am considering switching of owner ship with due care as you mentioned. It can be through IPC or with some flag interaction, CPU1 will indicate that it will be going to take owner ship of EMIF1. It will ensure that no task is pending from CPU2 when CPU1 wants to take owner ship(safe switching).
    Does signal EM1CLK will depend on which CPU is owning the EMIF1 peripheral? Will that have any disturbance in this safe switching? As this clk signal will be connected to FPGA IC.
    regards
    abhijit
  • 0 in reply to Abhijit Kelkar
    TI__Guru** 116971 points

    Hi Abhijit,

    Does signal EM1CLK will depend on which CPU is owning the EMIF1 peripheral? Will that have any disturbance in this safe switching?

    No, EM1CLK does not depend on which CPU is owning the peripheral so there will not be any disturbnance on this clock during ownership switching.

    Regards,

    Vivek Singh