phase drifting problem when two VSIs in parallel connection controlling by DSPs

Hi Lebing,

The PWMSYNCO and PWMSYNCI signal (a few GPIO pins can be configured to be these signals) are the best ways to synchronize two chips' PWMs.

With this scheme SYSCLK tolerance still has some impact, but it is usually not important enough to the system. To the system as long as the issues caused by tolerance can be bounded, things are generally okay.

Let's take the case where chip2 synchs to chip1. Chip1 will output a pulse on PWMSYNCO when PWM1's timer reaches 0 (note that the event choice is configurable). Chip2 will receive this signal and once the input is qualified Chip2's PWM will synch to Chip1's synch pulse. This means that Chip1 and Chip2's PWMs will each start at zero within ~one clock cycle (the ~1 cycle is to account for qualification). Assuming that SYSCLK is different on each chip due to tolerance, within a PWM period the difference between SYSCLKs will slowly accumulate. For example in the case where both chips trigger an ADC-SOC to occur when each chip's relevant PWM timer reaches 500, several SYSCLK cycles of delay may be seen between the two chips' ADC-SOC events. However, once PWM1's timer on chip1 reaches 0 again, chip2's PWM1 will again resynch and the accumulated error will reset at 0. Note that the worst case amount of cycles seen between two chips' ADC-SOCs could be reduced as more and more precise clock sources are used to generate each chip's SYSCLK.

Hopefully the above makes sense and helps you.


Thank you,
Brett