TMS320F28335 Example Circuit: Power Sequencing 3.3V and 1.9V

When I initially start a post thread, the Use rich formatting is not available.  It's only available in subsequent post.  Also, the drag and drop doesn't work. When I drag and drop a png file into the text box, a new browser tab opens showing file:///C:.... (i.e. the location of the png file

Ok. After calling TI, I solved the forum posting issue. For some reason, my E2E Profile E2E Options Content Editor setting was set to text instead of enhanced. 

The Power sequencing circuit is shown below.  Does anyone see any issues with it?  The Oscilloscope screenshot is shown below it.

 Green = 5V, Blue=3.3V and Orange = 1.9V.

 Green = 5V, Orange=3.3V and Blue = 3.3V Regulator Enable.

Seems fine but I would like you to refer this extract from the device datasheet: esp. the 3.3V & 1.9V part

Regards,

Gautam

Yes, specifically the last two sentences of the first paragraph:

"However, if the 3.3-V transistors in the level shifting output buffers of the I/O pins are powered prior to the 1.9-V transistors, it is possible for the output buffers to turn on, causing a glitch to occur on the pin during power up. To avoid this behavior, power the VDD pins prior to or simultaneously with the VDDIO pins, ensuring that the VDD pins have reached 0.7 V before the VDDIO pins reach 0.7 V."

Quote from Gautam:

"Seems fine but I would like you to refer this extract from the device datasheet: esp. the 3.3V & 1.9V part"

I am not exactly sure what you mean.  My original post on this thread stated that I was trying to follow that part of the data sheet.  

It's not fine since the power sequencing circuit I am using is not working, as can be seen by the oscilloscope images I posted.

Stephen

Stephen,

I am not too sure, but have some ideas on how to debug further (perhaps some you've already done):

I'd personally start with (1) and then move forward.

1) If this is a custom board, have you tried pulling off the LDOs, adding some flying leads, and powering the MCU & associated circuitry with external power supplies?  I have personally chased this type of issue several times now and often the power supplies aren't the problem.

2) It may be worthwhile to add a small capacitor (maybe a few 10s of pF) on the EN of the TPS79633 LDO with the intent of potentially limiting switching noise on the EN line.  You could probably put it on top of your 4K7 resistor for now.  This capacitor may not change anything, but if you see any change in behavior you may now have somewhere to look.

3) The ramp-y-ness of the TPS79633's EN pin near the region where it turns on may be another potential thing to look into.  Making your 4K7 pull-up resistor stronger, or changing the second switch from BJT to an appropriate MOSFET may improve things.


Thank you,
Brett

Hello Brett,

What is the purpose of  #1 above.  I am not having any issues with my system. I am just wanting to make sure the 1.9V comes up first.

Adding a 33pF capacitor across the 4.7kOhm resistor didn't change anything.

Also, I have already changed the 2nd BJT to a mosfet (FDV301N) and that didn't change anything.

Stephen

Hi Stephen,

Okay, I'm thinking that I missed the purpose behind your post.  Let me try to verify my new understanding of the situation...

Your system is working as expected and things are okay - the JTAG connects, flashing the MCU is fine, etc.  You've also seen no issues in your system.  The main intention of your post is to try to bring the system into agreement with the datasheet specifications for power sequencing.

Am I correct?  If so, then I was off in my previous post.

Moving to my new understanding: What does the 1V9 line look like in your second oscilloscope screenshot?  My feeling is actually that your system may be fine as it was (ie the 1V2 is ramping first and then the 3V3 ramps later).  I think your concern is coming because you're seeing voltage on the 3V3 line before you're enabling it.  You should note that there are some parasitic paths in the device such that the 1V9 rail may be partially powering the 3V3 rail before the 3V3 regulator is turned on.  Because this voltage on the 3V3 rail is coming from the 1V9 line is therefore coincident - and will therefore meet the wording of the specification.

Does this make sense or am I still missing something?


Thank you,
Brett

Hello Brett,

That's correct - there are no issues with the system.

As shown in  the first oscilloscope trace I posted, the 1.9V output  (orange trace) is 0V until 3.3V almost reaches 0.8V.  Therefore, I would say the 1.9V is not coincident with 3.3V since it doesn't come on at the same time as 3.3V.

If 1.9V is somehow partially powering the 3.3V rail, wouldn't the 1.9V output show something greater than 0V?

Stephen

Hi Stephen,

Sorry for the delay.  However, with the break I think I see your question more correctly.

I think the crux of your issue lies with, "why is the 3.3V line ramping early?".

I would recommend pulling off the TPS79633 and seeing if voltage still gets sourced onto the 3.3V line prior to the 1.9V line coming on (this will also allow you to see how the power sequencing circuit works on its own without a load). 

If the 3.3V still ramps, you know to look at other circuitry on the board.  This could be a number of things, but could also be the C2000 (if say one of its GPIO pins is pulled high before the chip is enabled). 

If it does not, then your intuition was right and the issue likely lies in the power sequencing circuit.  In this case, my guess is that 5V is going into the EN pin and starting to turn on the LDO before the 2nd FET turns on to pull EN to GND.  If this is the case, your best option may be to redesign to have EN come out of the emitter side of a FET which pulled to GND and controlled by 1.9V.  The other option is to find a FET with a "low enough" turn on voltage such that the EN line will be pulled low for a while prior to the 1.9V regulator turning on (and 3.3V always stays less than 0.7V during this time).

Hopefully this helps.


Thank you,
Brett

"I would recommend pulling off the TPS79633 and seeing if voltage still gets sourced onto the 3.3V line prior to the 1.9V line coming on (this will also allow you to see how the power sequencing circuit works on its own without a load). "

That sounds like a good idea, however, do you actually mean pulling up the TPS79501 (outputs 1.9V) instead of the TPS79633?  

I don't have time to do it know, but I will in the near future.

"If it does not, then your intuition was right and the issue likely lies in the power sequencing circuit.  In this case, my guess is that 5V is going into the EN pin and starting to turn on the LDO before the 2nd FET turns on to pull EN to GND.  If this is the case, your best option may be to redesign to have EN come out of the emitter side of a FET which pulled to GND and controlled by 1.9V.  The other option is to find a FET with a "low enough" turn on voltage such that the EN line will be pulled low for a while prior to the 1.9V regulator turning on (and 3.3V always stays less than 0.7V during this time)."

According to the scope trace, shown in my previous post the 3.3V regulator enable is near zero volts when the 3.3V regulator output is ramping up, so I am suspecting the FETs not the problem.

Stephen

"That sound like a good idea, however, do you actually mean pulling up the TPS79501 (outputs 1.9V) instead of the TPS79633?

[BL] No, I was meaning to take off the 3.3V regulator.  This would completely isolate it from being the device ramping the 3.3V early.  Taking the 1.9V regulator off instead/as-well may also be enlightening though.


"According to the scope trace, shown in my previous post the 3.3V regulator enable is near zero volts when the 3.3V regulator output is ramping up, so I am suspecting the FETS not the problem."

[BL] That's valid.  You're probably right.



Thank you,
Brett