Slope compensation and max duty cycle f28027

Hi David,

- Given the DAC settling time of the F28027, are there some limits on the duty cycle we can use? In other words, assuming that we use an amplified current sense signal with max amplitude 1.5v, how much time is needed for the DAC to reset from low to high at the end of the switching cycle?

There is no restriction on the duty cycle values. It is not expected that the system will suddenly go from one end of the duty cycle values in one PWM cycle to the other extreme in the next cycle. In addition to the DAC value reset at the PWMSYNC event (typically at the end of the switching cycle), this reset is also initiated when the comparator output goes active (i.e. peak current threshold is hit). This means that the DAC reset is initiated before the end of the PWM cycle in cases where the peak current threshold is hit. If the peak current threshold is not hit, the DAC reset will happen at the PWMSYNC event.

 - Is it possible to implement a ramp that does not start decrementing until later in the switching cycle? In other words, we probably need to implement a ramp that is flat until about 75% of the switching period, and then has a fairly steep slope, in order to implement an absolute current limit, and because otherwise the DAC would have to start the switching cycle at a value greater than the 100% of the reference voltage.

This is possible by using a different (unused) PWM module timer resource in the device that is sync'ed with and has an appropriate phase shift with respect to the PWM time-base used to control the power stage. The PWMSYNC event, which enables the ramp decrement, can then be generated using this spare PWM module at any point in the primary PWMs switching cycle by simply adjusting the phase shift between the two PWMs.

I hope this helps.

Hrishi