ADC Conversion Time calculation based on prescalers for TMS320F28335 Microcontroller

Hi Satya,

satya sudhir sure said:

So, Conversion time is 0.16us for both the channels. Please correct me...????

Nope, the conversion time would be much higher!

Here's a similar query, refer this link:

Let me know if you still have any doubts.

Regards,

Gautam

I am not clear with the link you have sent. Can you plz illustrate the way of calculating the ADC Conversation rate...
Please help me out Gautam.

Hi Satya,

  Even without making use of simultaneous sampling, a throughput of 12.5MSPS can be achieved in continuous sampling mode due to pipelining of the ADC.  The Autoconversion Sequencer Principle of Operation section of the TMS320x2833x Analog-to-Digital Converter (ADC) Module Reference Guide shows timing diagrams for both sequential and simultaneous modes of operation.  From the first diagram in subsection Sequential Sampling Mode, it can be seen that when multiple conversions are performed and ACQ_PS is set to zero, the results of subsequent conversions are available two ADCCLKs after the previous conversion. (please note the rightmost vertical dashed line should be shown on the previous rising edge, this is a typo I will submit for correction).

  Using sequential sampling mode, for every cycle added to ACQ_PS there will be one additional cycle is added to the total conversion time so the effective throughput of continuous conversions would be 1/[[2+ACQ_PS]*ADCCLK(ns)] so for example:

ADCCLK=40ns (25Mhz), ACQ_PS=0, the throughput would be 12.5MSPS

ADCCLK=40ns (25Mhz), ACQ_PS=3, the throughput would be 5.0MSPS

  When utilizing simultaneous sampling mode there is further benefit in that the subsequent pairs of conversions can be obtained four cycles after the previous pair but increases to ACQ_PS will add one cycle for every two conversions.  You could say each pair will be available 1/[[4+ACQ_PS]*ADCCLK(ns)] so for example

ADCCLK=40ns (25Mhz), ACQ_PS=0, the throughput would be 12.5MSPS

ADCCLK=40ns (25Mhz), ACQ_PS=3, the throughput would be 7.1MSPS

Please note for simplicity I calculated when both conversions of the simultaneous pair are available, however "C1" will be available one ADCCLK prior to C2.

I hope this helps,

Joe

Joe,

Can you please explain me what do you mean by 12.5 MSPS or 7.1 MSPS.

So, can I go ahead considering the ADC conversion time formula when configured in Simultaneous sampling mode is (4+ACQ_PS) * ADCCLK.

Please clarify me at the earliest.

My observations:

HISPCP Prescaler - 3

ADCLKPS Prescaler - 0

CoreClock Prescaler - 0

Acquisition window Prescaler - 0x2F

Moreover, ADC is configured in Cascaded & Simultaneous mode

Max no of Cascaded conversions is 0x2.

Applied input - 5KHz Sine Wave (200 Microsecs for 1 cycle)

With the above configuration,

I obtained 150 samples for 1 complete cycle of 5KHz sinewave.

 

So, if I apply your formula in this scenario i.e., (4+47)*0.04 = 2.04 Microseconds.

No of samples = 200 (us)/2.04 (us) = 100 samples (approx.,)

 

Can you please clarify accordingly as early as possible.

Regards,

Satya Sudhir Sure

 

Hi Satya,

  MSPS stands for Mega-Samples-Per-Second (or Million-Samples-Per-Second) and is a way to demonstrate the throughput of the ADC.  For C2000 devices we typically specify this number based on the minimum time at which conversions results will be made available when continuously converting (which takes advantage of the conversion pipeline).

  After the initial conversion, the F28335 ADC can provide a new conversion result every two ADCCLKs, so at the maximum ADCCLK of 25MHz, continuous conversions at the rate of 12.5 million samples per second can be obtained.

  In your particular situation, the sample window is increased so that throughput is not achievable, but based on the signal you are sampling also not required.  If you are using continuous conversion mode (CONT_RUN) then you should effectively get 1-pair of conversions every (4+47)*40ns = 2.04us as you calculated.

  If you are not running in continuous sampling mode, but rather triggering the ADC, for example using a PWM, then every SOC will only generate three pairs of conversions since MAXCONV=0x2.  In this case the latency of the first sample in the sequence will no longer be negligible and needs to be factored in.  You should be able to use the timing diagrams mentioned in the previous post to determine what the impact would be.  Also the total number of samples obtained in one of your sinewave cycles would be determined by your triggering rate.

I hope I have clarified your questions, if so please verify my answer below!

Regards,

Joe

Joe,

I already stated in my earlier conversation that I have configured ADC in Continuous run mode for which trigger is required only once at the start.

I am triggering ADC SOC through software only once. Even though I was unable to achieve the desired number of samples. Instead, I am getting more samples.

 

Can you please clarify??

 

Thanks & Regards,

Satya Sudhir Sure

Satya,
If I understand your concern, you are sampling for one cycle of your input signal which is 5kHz and expecting ~100 ADC samples but seeing ~150 samples. Presumably you are copying the ADC results to somewhere for analysis, how is this done? Does the 150 samples appropriately reconstruct your input signal or does it have signs of aliasing?

If the former, can you confirm the SYSCLK = 150Mhz by observing XCLKOUT or toggling a GPIO?
If the latter, could your method of copying ADC results be copying data faster than ADC results are updated, so you are getting duplicate data?