TMS320F280x 60Hz EPwm clock Prescaling

Harsh

Hello,

I want to use Epwm to generate a 60Hz Pwm. So I'm trying to prescale the Clock using HSPCLKDIV and CLKDIV fields of the TBCTL Register.

I am able to use TB_DIV4. IS it possible to further scale it down, say to TB_DIV5 ?

My understanding is TB_DIV4 is 100MHz/ 2^4 = 6.25MHz. Is that right ?

Thank you

Regards,

Harsh

over 11 years ago

0 Subrahmanya over 11 years ago

TI__Mastermind 24095 points

Harsh,
EPWM Clock can be scaled down using HSPCLKDIV and CLKDIV fields.

EPWMCLOCK = 100MHz/ (HSPCLKDIV * CLKDIV)

Note that these dividers mean different divide values. Bit definition is below -

HSPCLKDIV:
000: /1
001: /2 (default on reset)
010: /4
011: /6
100: /8
101: /10
110: /12
111: /14

CLKDIV:
0,0,0 /1 (default on reset)
0,0,1 /2
0,1,0 /4
0,1,1 /8
1,0,0 /16
1,0,1 /32
1,1,0 /64
1,1,1 /128

0 Harsh over 11 years ago in reply to Subrahmanya

Prodigy 220 points

Hello Bharathi Subrahmanya,
Thank you for the reply.

Can you please explain it with one example, for example with EPWMCLOCK = 2.5MHz and the values for HSPCLKDIV and CLKDIV. I did find these formulas, but I wasn't able to get the computation behind it. Please help me out.

Thank you

Regards,
Harsh

0 Subrahmanya over 11 years ago in reply to Harsh

TI__Mastermind 24095 points

Harsh,2.5MHz can be achieved by
HSPCLKDIV = 0x5 //i.e b'101 => implies div by 10
CLKDIV = 0x2 //i.e. b'010 => implies div by 4

0 Harsh over 11 years ago in reply to Subrahmanya

Prodigy 220 points

Hello Bharathi Subrahmanya,
That makes Sense. Thank you for explaining in detail.
Thank You.

Regards,
Harsh

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TMS320F280x 60Hz EPwm clock Prescaling