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TMS320F28035 ADC Timings for different acquisition window size

Other Parts Discussed in Thread: TMS320F28035

Hi there,

 I need some help calculating ksps on TMS320F28035.

 The ADC manual shows the ADC Timing Diagrams in section 1.11. This diagrams have been made for 7Clk Acq. Window and do not clearly show how the timing would change if the Acq window size changes.

 Could you please help me calculating the ksps for 14 samples in simultaneous mode with Acq. Window size of 55? The ADC samples are being triggered by a PWM module every 70kHz.

 Thanks,

Lucas

  • Lucas,

      For simultaneous sampling and assuming you are using OVERLAP mode, I think the simplest way to look at it is like this, where the numbers represent ADCCLKs:

      When using OVERLAP mode, the first seven ADCCLKs of sampling are being performed in parallel with the previous sample's conversion.  If ACQPS=6 (7 ADCCLKs) then subsequent conversions are effectively back to back conversions with sample time for free.  For every cycle increase in ACQPS this will increase the total sample time per pair by one ADCCLK.  The first pair will take (ACQPS+1)+13+13, but subsequent pairs will take ((ACQPS+1)-7)+13+13.

      So when ACQPS = 54 (55 ADCCLKs) the total time for the first pair is 81 ADCCLKs and subsequent pairs will be 74 ADCCLKs.

      Keep in mind when OVERLAP mode is not being used there is no pipeline affect so the total conversion time per pair is always (ACQPS+1)+13+13.

    I hope that helps!

    Joe

  • Thanks Joe, that helps!

    Therefore, according to what you said, if I use sequential sampling with overlap I will have a first sample in 68ADCCLKs and subsequent samples in 61ADCCLKs. Is that correct?

    Lucas