Dear support,
We have to use GPIO 128-135 in concerto C28 (F28M35H52C1). We use all definitions per technical doc, but it doesn't work.
EALLOW;
GpioG2CtrlRegs.GPEMUX1.bit.GPIO128 = 0; //A0 OUT/in general purpose I/O 128
GpioG2CtrlRegs.GPEMUX1.bit.GPIO129 = 0; //A1 OUT/in general purpose I/O 129
GpioG2CtrlRegs.GPEMUX1.bit.GPIO130 = 0; //A2 OUT/in general purpose I/O 130
GpioG2CtrlRegs.GPEMUX1.bit.GPIO131 = 0; //A3 OUT/in general purpose I/O 131
GpioG2CtrlRegs.GPEDIR.bit.GPIO128 = 1; // A0 OUT Configures the GPIO pin as an output
GpioG2CtrlRegs.GPEDIR.bit.GPIO129 = 1; // A1 OUT Configures the GPIO pin as an output
GpioG2CtrlRegs.GPEDIR.bit.GPIO130 = 0; // A2 IN* Configures the GPIO pin as an input
GpioG2CtrlRegs.GPEDIR.bit.GPIO131 = 0; // A3 IN * Configures the GPIO pin as an input
EDIS;
//set io to 1:
GpioG2DataRegs.GPESET.bit.GPIO128 = 1;
GpioG2DataRegs.GPESET.bit.GPIO129 = 1;
//Delay 100usec
//set io to 0:
GpioG2DataRegs.GPECLEAR.bit.GPIO128 = 1;
GpioG2DataRegs.GPECLEAR.bit.GPIO129 = 1;
val = GpioG2DataRegs.GPEDAT.bit.GPIO130; //read value A2
We don't see any changes in IO by using above commands.
Couls you help ua with? what wrong here?
m3 part:
HWREG(SYSCTL_MWRALLOW) = 0xA5A5A5A5;
// Setup main clock tree for 75MHz - M3 and 150MHz - C28x
SysCtlClockConfigSet(SYSCTL_SYSDIV_1 | SYSCTL_M3SSDIV_2 | SYSCTL_USE_PLL | (SYSCTL_SPLLIMULT_M & 0x0F));
// Disable clock supply for the watchdog modules
SysCtlPeripheralDisable(SYSCTL_PERIPH_WDOG1);
SysCtlPeripheralDisable(SYSCTL_PERIPH_WDOG0);
IntMasterEnable();
SysCtlPeripheralEnable(SYSCTL_PERIPH_GPIOE);
SysCtlPeripheralEnable(SYSCTL_PERIPH_GPIOF);
SysCtlPeripheralEnable(SYSCTL_PERIPH_GPIOG);
GPIOPinConfigureCoreSelect(GPIO_PORTE_BASE, 0xFF, GPIO_PIN_C_CORE_SELECT);
We tried to comment the last line: GPIOPinConfigureCoreSelect(GPIO_PORTE_BASE, 0xFF, GPIO_PIN_C_CORE_SELECT); , but it didn't affect.
GpioG2DataRegs doesn't changed.
Thanks, Sabina
