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Piccolo ADC



Hereby a question regarding the ADCs in the Piccolo.

If you look at figure 32 in SPRUGE5B (TMS320x2802x, 2803x Piccolo Analog-to-Digital Converter (ADC) and Comparator reference guide) it shows that the Sample Holds are sampling SOC2 while the ADC is converting SOC0. How is it possible to sample when the SH circuit are sampling a new value. Will the new sampling not change the value on the SH capacitor and that way interrupt the conversion (which is using the value to convert)?

  • If you look at figure 1 you will see that there are two independent Sample and Holds that feed a 2 input mux prior to the conversion. This allows one to be sampling while the other is converting or more importantly (sometimes) to take two samples from different channels at the same instant.

  • Yes.

    But if you look at figure 32 the ADC module is sampling both input A and B while converting B.

    Meaning, the part is converting channel B and sampling Channel B at the same time...

     

  • I believe that conversions always start on the falling edge SOC as shown in the diagram. The actual conversion cycle is always 13 clocks and the internal pipeline and delays are such that it needs the previous sample to be stable for only the first 6 cycles of the conversion. This allows you to run back to back conversions every 13 clocks and an a/b pair every 26 clocks.