I am using an F28377D to do peak current mode control of a phase-shifted full-bridge. It works quite similar to the scheme described in "PSFB Control Using C2000
Microcontrollers" (SPRABR1). My problem is that sometimes after the voltage is removed from the transformer, the current takes a while to decay and can bleed into the following switching cycle. This can cause problems with the comparator trip. I'm trying to get around this using the blanking window feature of the digital compare
submodule, but it doesn't appear to be working the way I'd expect (or at all).
Here are some specific questions I have. The page numbers and figures refer to SPRUHM8C (TMS320F2837xD Dual-Core Delfino Microcontrollers Technical Reference Manual).
- If the blanking window is configured and enabled, is there anything that would prevent it from having an effect? As a test I've configured the offset and window length such that the entire cycle should be "blanked," but regardless of what I do it has no effect on whether (and when) the comparator trips happen.
- Is there an app note or a diagram that clearly explains the configuration of the "trip logic" in Figure 13-41? There are a lot of registers there, some of which are not described very clearly (or at all) in the documentation. I'm particularly confused about the interaction between the digital compare and the trip-zone submodules. Also, although it is implied that setting TZCTL2.ETZE = 1 means settings in TZCTL are ignored, I'm not convinced this is really the case.
- Are events ignored when the blanking window signal is high or low? The English description on pp. 1535-1536 and Figure 13-55 suggest that events are ignored when the blanking window is high, but in Figure 13-54 the BLANKWDW signal going into the MUX, which is then ANDed with the DCxEVTy signals, suggests that the event is filtered out unless the blanking window is high.
- Is DCFWINDOW 16 bits or 8 bits? I've found posts on E2E suggesting that (at least for older parts) it's 8 bits, and the "01-FFh" mentioned in the description on page 1657 suggests it's 8 bits in the '377, but the register itself is shown as having 16 valid bits.
- Are there propagation delays between the comparator subsystem, PWMSYNC, and PWM digital compare/trip-zone modules that need to be accounted for?
Thanks in advance for any insight anyone can provide.
