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TMS320F28027 Comparator Module: PWM sync signal and system clock correct timing.

sp1986MM
Prodigy 30 points

Other Parts Discussed in Thread: TMS320F28027

Hello, in the "spruge5f.pdf" - ADC and Comparator Reference guide, on page 46 i read:

"The PWMSYNC signal width must be greater than SYSCLK to ensure that the ramp generator is able to detect the PWMSYNC signal."

From page 101 on the TMS320F28027's Datasheet I see the requirement for the PWM synch clock is a minimum of 2 system clock cycles

Simply, how can I set PWMSYNC to make sure the timing is correct?

Many thanks!

  • 0
    TI__Mastermind 24095 points

    Hi,

    These 2 signals in 2 documents are different.

    Page 101 on the TMS320F28027's Datasheet:
    The Sync In timing requirement of 2 Systtem clock cycles is if you are using (tw(SYCIN) Sync input pulse width) external signal as Sync Input to Sync the PWM modules.

    PWMSYNC in spuge5f:
    This is the PWMSYNC signal used to reset DAC ramp generator. This signal is generated by EPWM module and pulse width is 1 EPWM clock cycle.

    -Bharathi