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F28035 ADC with CLKDIV2EN = 1 and NONOVERLAP = 1

Pierre Bouchet1
Expert 2615 points

Hi everyone,

I want to use the ADC setting the CLKDIV2EN and NONOVERLAP bits as recommended in the Silicon Errata (under ADC: Initial Conversion)

In the ADC datasheet (SPURGE5F) the text on Figure 37 states the following:

In this timing ADC Sample window need not hold to 7 ADC clocks minimum.


Moreover this is written in Table 4 (ADCCTL2):

When running /2 ADCCLK scale the minimum sample duration accordingly to meet 116.6ns for better throughput.


So, does all this mean that I can write a value smaller than 6 to ACQPS? E.g if I write 3 it will mean 4 cycles and with ADCCLK at 30MHz this yields a sample window of 4/30MHz = 133ns ?

Best Regards,

Pierre

  • 0
    TI__Guru 60865 points
    Hi Pierre,

    I am looking into this. At the moment, it appears that the ADC user guide and the datasheet are in conflict (UG says you can use S+H < 7 ADCCLKs under some circumstances, DS says you must use S+H > = 7 ADCCLKs). In these situations, the DS always takes precedence (and my understanding is that you can't use S+H < 7 ADCCLKs even when using ADCCLK = SYSCLK / 2, but I will confirm this).
  • 0 in reply to Devin Cottier
    TI__Guru 60865 points
    Hi Pierre,

    I have confirmed that you should use S+H >= 7 ADCCLKs under all circumstances. I will update the ADC UG to remove any confusion.