ADC interrupts from SEQ1INT, SEQ2INT and ADCINT

Hi Gautam,

Yes you are right, I am using F28335. I have already checked ADCST register. Interrupt flags are set after EOC. So the interrupt from SEQ1 or SEQ2 occured. The problem is that doesn't metter which SEQ1 or SEQ2 caused the interrupt, the interrupt vector always starts from ADCINT(INT1.6), but not from SEQ1(INT1.1) or SEQ2 (INT1.2). In standard libruary it looks like next:

I want to be in INT1.1 or INT1.2. But I always end up in INT1.6, in spite of the priority of interrupts form SEQ1 and SEQ2 which is higher than ADCINT. 

// INT1.1
interrupt void SEQ1INT_ISR(void) //SEQ1 ADC
{
// Insert ISR Code here

// To receive more interrupts from this PIE group, acknowledge this interrupt
// PieCtrlRegs.PIEACK.all = PIEACK_GROUP1;

// Next two lines for debug only to halt the processor here
// Remove after inserting ISR Code

// asm (" ESTOP0");
EALLOW;
GpioCtrlRegs.GPBDIR.bit.GPIO34 = 1;

for(;;);

}

// INT1.2
interrupt void SEQ2INT_ISR(void) //SEQ2 ADC
{

// Insert ISR Code here

// To receive more interrupts from this PIE group, acknowledge this interrupt
// PieCtrlRegs.PIEACK.all = PIEACK_GROUP1;

// Next two lines for debug only to halt the processor here
// Remove after inserting ISR Code

EALLOW;
GpioDataRegs.GPBSET.bit.GPIO34 = 1;
for(;;);

}

// INT1.6

interrupt void ADCINT_ISR(void) // ADC
{
// Insert ISR Code here

// To receive more interrupts from this PIE group, acknowledge this interrupt
// PieCtrlRegs.PIEACK.all = PIEACK_GROUP1;

// Next two lines for debug only to halt the processor here
// Remove after inserting ISR Code

EALLOW;
GpioDataRegs.GPBSET.bit.GPIO34 = 1;
for(;;);

}