Hi
Do you have data to estimate interrupt latent from DMA block finishing it work writing DRR data from McBSP into RAM (ie when it completed transfer-size (say 512 word 32 bits)).
It quoted 14 clock cycle minimum, does it mean less than 14 clock cycle?, does this apply to McBSP/DMA or was is zero latent interrupt?
I have 12MHz serial stream into McBSP and F28335 running on 60MHz SYSCLK (to keep power down). The data is 24 bits which invoke DMA transfer to L4RAM. I assumed the latent delay is 1 clock cycle due to pipeline as datasheet indicated.
Thanks
R.
