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TMS320F2812 XCLKIN Duty Cycle

Peter Fritzenschaft
Intellectual 381 points
Other Parts Discussed in Thread: SN74LVC1G14

The data manual SPRS174T requires a duty cycle of 40/60% on XCLKIN.

When using an oscillator with 3.3V Output , the design Guidelines document SPRAAS1B recommends using a Schmitt-Trigger Inverter SN74LVC1G14 to convert the clock Level to 1.9V. The threshold of SN74LVC1G14 is at about 0.9V, which leads to an additional shifting of the duty cycle.

So when I have an oscillator duty cycle of 48/52%, this already leads to a duty cycle  of 39/61 on XCLKIN pin which is not compliant to the 40/60 requirement.

Can this lead to a wrong System clock, or is the duty cycle uncritical because the PLL synchronizes on only one edge of the clock Signal?

  • 0
    TI__Guru* 80470 points
    Peter,
    Can you comment on the clock frequency of the oscillator you are using? The Duty requirement is coming from a pulse width requirement to detect rising/falling correctly. This device allows 150MHz direct clock, so if you are using something slower and multiplying up with the PLL you should be OK at 39/61 you mentioned.

    Matt
  • 0 in reply to MatthewPate
    Intellectual 381 points
    Hello Matt,

    we use a 30MHz oscillator and multiply it up to 150MHz.

    So when you mention a 150MHz direct clock (6.66ns cycle time), I would consider a pulse width of >3ns as acceptable limit also for slower clocks (as long as the slew rate requirement < 6ns is fulfilled)?

    Regards, Peter