Shared RAM wait states

Hi Naveen,

Section 5.1.1.5 of F28M35 TRM will give you a brief idea:

5.1.1.5 Access Timing
In general on these devices, all RAM blocks have one cycle access time; that is, if there is only one
access and no other access is pending to that particular RAM block. However, since there are different
types of shared RAMs, where multiple masters can access the same RAM block, that will not always be
the case.
Following are access cycle times in different scenarios:
• In case of M3/µDMA, a write access, immediately followed by a read access to the same RAM block,
incurs a stall of a single clock cycle.
• M3/µDMA write access can have one extra wait state in case of arbitration and M3/µDMA access does
not win during arbitration cycle.
• Max cycle latency for an access to Sx memory from any master is six cycles when M3 is master for
that Sx memory. The following are the possible accesses with details of how many cycles each access
takes.
– µDMA access – two cycles (reads or byte writes takes two cycles of C28 clock when M3 clock
config is /2 or /4 of C28 clock)

– M3 byte access – two cycles (reads or byte writes takes two cycles of C28 clock when M3 clock
config is /2 or /4 of C28 clock)
– C28 Read – 1cycle
– C28 Pread – 1 cycle
– C28 DMA Read – 1 cycle
• Max cycle latency for an access to Sx memory from any master is seven cycles when C28 is master
for that Sx memory. The following are the possible accesses with details of how many cycles each
access takes individually.
– µDMA Read access – two cycles (reads takes two cycles of the C28 clock when M3 clock config is
/2 or /4 of C28 clock)
– M3 Read access – two cycles (reads takes two cycles of the C28 clock when M3 clock config is /2
or /4 of C28 clock)
– C28 Read – 1 cycle
– C28 Pread – 1 cycle
– C28 Write – 1 cycle
– C28 DMA write/Read – 1 cycle

Regards,

Gautam

Naveen,

In summary, the answer to your question -

But i want to know whether shared ram is exactly like normal RAM and if there are any waitstates for shared ram ( if i access it only from one end i.e C28 ) when compared with normal RAM.

Yes, wait states for shared RAMs are exactly like normal RAM if accesses are made by one master only.

Regards,

Vivek Singh