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SCI FIFO Receive (SCIFFRX) Register

Andrew Butler
Expert 2520 points
Other Parts Discussed in Thread: CONTROLSUITE

I'm trying to read in a 45 Byte message with SCI FIFO. I have configured the SCI FIFO Receive (SCIFFRX) Register as follows:

    SciaRegs.SCIFFRX.all=0x2141;

I am only reading in one byte at a time because the FIFO can only read 16 Bytes at a time. However, since I am only reading one byte at a time, I am only catching 2 Bytes of the 45 Byte message. Is there anyway to receive a 45 Byte message without missing a Byte?

  • 0
    TI__Mastermind 32995 points

    Hi Andrew,

    SCI / UART is an asynchronous protocol. You will likely have to implement your own protocol to ensure data integrity. An example of this could be an echo-back protocol or an ACK/NAK protocol.

    I suggest using the 16 byte FIFO and try to read and store as much as you can.

    What device are you using? Are you using interrupt service routines?  You can increase the RXFFIL bit field to generate an interrupt after receiving a specific amount of bytes in the FIFO.  You can generate interrupts when the FIFO level has reached up to 16.

    Best Regards,
    sal

  • 0 in reply to Sal Pezzino
    TI__Guru* 87155 points

    Andrew,

    Also note that RXFFST indicates FIFO status (number of bytes received in FIFO) and are read-only bits.  I noticed that you are configuring those bits.

    You can configure RXFFIL so that CPU can receive an interrupt whenever the number of bytes received in FIFO (RXFFST) are greater than or equal to RXFFIL.  

    Thanks and regards,
    Vamsi

  • 0 in reply to Vamsi Gudivada
    Expert 2520 points
    Sal,

    I'm using sci interrupts with the F28069 launchpad.

    Vamsi,

    Can I set the RXFFIL >= 45 Bytes or am I limited to 16?
  • 0 in reply to Andrew Butler
    TI__Guru* 87155 points
    Andrew,

    SCI in F28069 has only 4-level deep FIFOs and not 16-level deep FIFOs.
    Hence, you can configure RXFFIL for a max of 4 only. As Sal suggested, you should implement a protocol for the communication so that you won't miss any data.

    Thanks and regards,
    Vamsi
  • 0 in reply to Vamsi Gudivada
    Expert 2520 points
    Sal,

    I am trying to interface with a GPS module and I don't believe it will be able to generate an ACK. Are there examples on how to implement an echo-back protocol or an ACK/NAK protocol with a F28069 launchpad?
  • 0 in reply to Andrew Butler
    TI__Mastermind 32995 points
    Andrew,

    Echo-back will receive a byte from the RX Buffer/FIFO, store it and send it back to via SCI TX Buffer/FIFO. An ACK/NAK can be used if you are expecting specific values or amounts of data to be received. If it is received properly then ACK. If it received improperly, then NAK, and re-send the data.

    We have an example in controlSUITE where we implemented a echo-back and ACK/NAK protocols to ensure correct timing and data integrity. Look at the F2837xD_sci_flash_kernels in device_support/F2837xD/v150/F2837xD_examples_Dual. The flash kernel echos-back every byte in the function SCI_GetWordData() in SCI_GetFunction.c.

    Also, in SCI_GetFunction.c you can see the functions SendNAK() and SendACK() and SCI_Flush().

    The flash kernels are very specific to using a SCI to load and program flash, but you can see how the communication is being done to ensure data integrity in this example. Also, keep in mind that this example is for the F2837xD and NOT the F28069x, and there are some differences in registers and bitfields.

    sal
  • 0 in reply to Sal Pezzino
    Expert 2520 points
    How does echo back ensure data integrity outside of the user monitoring whats being sent back out the transmit line?
  • 0 in reply to Sal Pezzino
    Expert 2520 points
    Do I have to use the FIFO register to generate an interrupt? Will I be able to get 45Bytes without using FIFO?
  • 0 in reply to Andrew Butler
    TI__Mastermind 32995 points
    It can help to ensure data integrity by monitoring the returned value to the host who is transmitting the characters. You are correct. The host must monitor what is being sent back.

    You need to configure SCICTL1.bit.RXENA = 1 and SCICTL2.bit.RXBKINTENA =1 to enable receiving and enable RX/BK interrupts. Then configure SCIFFRX.bit.RXFFIENA = 1; SCIFFRX.bit.RXFFIL = 4 so that it will generate an interrupt when the FIFO is full (4 levels max).

    You will not be able to get 45 bytes at one time. You can only receive a maximum of 4 bytes with the FIFO. When data is received, the module sets the RXRDY bit and you then need to read the data from SCIRXBUF.

    You can also receive data from the SCI without configuring interrupts:
    You can poll RXDY and wait to read one byte at a time from SCIRXBUF, and continue this until you have read all of your data. See below pseudocode...
    for i < 45
    while(RXDY != 1)
    data = SCIRXBUF.bit.RXDT;

    You still may need to adjust the timing of data being sent and received so that data is not lost. Hope this helps.

    sal