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More than one I2C own address? (per SMBus alert response protocol)

TobyM
Genius 5200 points

Hi folks,

I am attempting to implement an SMBus device (slave) over I2C on the F28027.

When a device generates an alert it raises a signal to the host (master) over an-out-of-band shared wired-AND GPIO line - #SMBALERT

When the host see's this line asserted it broadcasts an Alert Response to address 0x0Ch, which effectively acts as a second general call address with the special function that slaves that have asserted the alert respond with their own addresses.

I am wondering if it is possible to implement this, as the Alert Response address is effectively a third own-address (the first two being the device's own address and the general call address)

I had considered using the free data format to bit-bang the SMBus protocols and manage the addressing within the program instead of the hardware, but I believe that the constraint that

"the direction of the data must be constant throughout the transfer"

prevents the ability to match the SMBus protocols as the follow a scheme such as the following (where upper case = master & lower case = slave):

START - - ADDRESS - - W - - DATA BYTE - - ack - - REPEAT START - - ADDRESS - - R - - ack - - data byte - - NACK - - STOP

with the problem arising where a read is always preceded by an addressing.

Is there any other option to implement this on the F28027??

Many thanks.

  • 0
    Genius 5200 points

    Maybe I misunderstood the I2COAR register usage, can this be changed on the fly? or does the peripheral have to enter reset?

    EDIT: Seems like it can be changed on the fly... however this doesn't really solve the issue as a master doesn't necessarily HAVE to address the device using the 0x0ch address directly after the #SMBALERT assertion but may address it normally ... so if the device's own address has changed to meet the 0x0Ch address it would miss the messages to its normal address :(

  • 0 in reply to TobyM
    Genius 5200 points
    Does anyone know if it is possible to make the I2C peripheral believe it has received a condition (e.g. REPEATED START) when it really hasn't?
    I'm thinking that this is the only way I could achieve the required functionality on this device.

    If I use the free data format, then for the read portion of an SMBus protocol the master sends the addressing byte as normal. When the slave receives the first byte, the program expects it to be an addressing byte. If the address matches the own address or the Alert Response address and the 8th bit is equivalent to a master READ bit, the slave (and here's where my question comes in) forces its own I2C hardware to think it has received a following REPEATED START, then it can still use the free data format, but now it thinks it is at the start of a transaction and so can write data out to the master, thus changing direction.