Use of ADC EOC based interrupt overflow flag

Hi,

          I am using TMS320F28027 DSC. I am using ADCINT1, ADCINT2, SCI RX INT & SCI TX INT. 

The ADCINT1 trigger at EPWM1A PRD & ADCINT2 trigger at EPWM1B ZERO. In both ADCINT  what I found is ADCINTOVF flag set for multiple times. The implementation is as follows

if(1 == AdcRegs.ADCINTOVF.bit.ADCINT1)
{
AdcRegs.ADCINTOVFCLR.bit.ADCINT1 = 1;

adc_isr1_overflow_cntr++;
}

&

if(TRUE == AdcRegs.ADCINTOVF.bit.ADCINT2)
{
AdcRegs.ADCINTOVFCLR.bit.ADCINT2 = 1;

adc_isr2_overflow_cntr++;
}

I check this implementation in main loop at the rate of 3mili second.

And I check adc_isr1_overflow_cntr & adc_isr2_overflow_cntr on MODBUS communication where I found these counters are incrementing.

So my doubt is:

1. what will happen if i does't clear ADCINTOVF bit .
2. In my implementation if these overflow_cntr  continuously increased what could be impact on ADCINT

  Well i've checked both cases but didn't found anything problematic at all. But I am curious to know about impact of this ADCINTOVF  flag on ADCINT generation and the usage of this ADCINTOVF  .