Other Parts Discussed in Thread: CONTROLSUITE
In the 2837xD technical reference (SPRUHM8C–December 2013–Revised December 2014), table 12-5 lists the Shift Control Bit Configuration Settings versus OSR and filter used.
The table does not clearly state whether the OSR column is the actual OSR or the OSR register setting -- I assume it is the actual OSR because 256 is the last entry, which is the maximum obtainable OSR.
I have my Sigma Delta circuit working at OSR = 25, and I am using the latest ControlSuite sdfm_pwm_sync_cpu_cpu01 sample code, so I believe the registers are being set correctly.
However if I set to OSR=50 (SDDFPARM1.DOSR=49), using sync3 filter, and if I set the Shift Control bit setting to 2 (from the "OSR from 41 to 50" row), I measure twice the actual value -- and it works again if I set the Shift Control bit value to 3, which is from the "OSR from 51 to 63" row.
Is it possible your table is in error on the boundary conditions -- that the OSR=50 should correspond to the SDIPARM1.SH=3 row?
Thanks,
Jim
