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Is it possible that the assignment instruction would be interrupted by another ISR?

Fei Pan
Intellectual 620 points

Hi All,

I am using F28377D. For example, I have two global float variables, A and B. In one lower priority ISR, I have one instruction A = B. For some reason, another higher priority ISR would interrupt this lower priority ISR, and it needs to read the correct data of A. When the CPU do A = B, I guess at first the lower 16 bits of B would be assigned to the lower 16 bits of A. If the higher priority ISR interrupts it at this time, then the read value of A would be wrong because the higher 16 bits data is not correct. Is my understanding correct?

Thanks

  • 0
    TI__Mastermind 24095 points
    Fei,

    CPU supports 32-bit data operations/movement.
    Having said that - In general, If you want to certain sequence of code to be non-interruptible, you can do so by by disabling the global interrupt (DINT) and enable the same (EINT) after the sequence.

    -Bharathi.