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28027F.cmd file not correct

Other Parts Discussed in Thread: MOTORWARE

In the InstaSpin FOC projects the 28027F.cmd file is incorrect or I am missing something.

It appears the 28027 thinks its a 28026

FLASHA_D    : origin = 0x3F4000, length = 0x007F80 //WRONG for 28027

Should be

FLASHA_D    : origin = 0x3F0000, length = 0x007F80 

I started getting Flash programming Errors even though CCS compiled OK.

I seen other post about this and still the bug exists in the latest Motorware.

Is this change correct or is there more changes required to fix this problem.

Is the length correct in my above change?

  • Gary,

    Correct. I think this was discussed here earlier this year. It is fixed and will be in next version of motorware.

    I'll attach the file tomorrow, not at my laptop at the moment.

  • /*
    // TI File $Revision: /main/7 $
    // Checkin $Date: July 6, 2009   17:25:36 $
    //###########################################################################
    //
    // FILE:	F28026.cmd
    //
    // TITLE:	Linker Command File For F28026 Device
    //
    //###########################################################################
    // $TI Release: 2802x C/C++ Header Files and Peripheral Examples V1.29 $
    // $Release Date: January 11, 2011 $
    //###########################################################################
    */
    
    /* ======================================================
    // For Code Composer Studio V2.2 and later
    // ---------------------------------------
    // In addition to this memory linker command file,
    // add the header linker command file directly to the project.
    // The header linker command file is required to link the
    // peripheral structures to the proper locations within
    // the memory map.
    //
    // The header linker files are found in <base>\DSP2802_Headers\cmd
    //
    // For BIOS applications add:      DSP2802x_Headers_BIOS.cmd
    // For nonBIOS applications add:   DSP2802x_Headers_nonBIOS.cmd
    ========================================================= */
    
    /* ======================================================
    // For Code Composer Studio prior to V2.2
    // --------------------------------------
    // 1) Use one of the following -l statements to include the
    // header linker command file in the project. The header linker
    // file is required to link the peripheral structures to the proper
    // locations within the memory map                                    */
    
    /* Uncomment this line to include file only for non-BIOS applications */
    /* -l DSP2802x_Headers_nonBIOS.cmd */
    
    /* Uncomment this line to include file only for BIOS applications */
    /* -l DSP2802x_Headers_BIOS.cmd */
    
    /* 2) In your project add the path to <base>\DSP2802x_headers\cmd to the
       library search path under project->build options, linker tab,
       library search path (-i).
    /*========================================================= */
    
    /* Define the memory block start/length for the F28026
       PAGE 0 will be used to organize program sections
       PAGE 1 will be used to organize data sections
    
       Notes:
             Memory blocks on F2802x are uniform (ie same
             physical memory) in both PAGE 0 and PAGE 1.
             That is the same memory region should not be
             defined for both PAGE 0 and PAGE 1.
             Doing so will result in corruption of program
             and/or data.
    
             The L0 memory block is mirrored - that is
             it can be accessed in high memory or low memory.
             For simplicity only one instance is used in this
             linker file.
    
             Contiguous SARAM memory blocks or flash sectors can be
             be combined if required to create a larger memory block.
    */
    
    MEMORY
    {
    PAGE 0:    /* Program Memory */
               /* Memory (RAM/FLASH/OTP) blocks can be moved to PAGE1 for data allocation */
    
       OTP         : origin = 0x3D7800, length = 0x000400     /* on-chip OTP */
       CSM_RSVD    : origin = 0x3F7F80, length = 0x000076     /* Part of FLASHA.  Program with all 0x0000 when CSM is in use. */
       BEGIN       : origin = 0x3F7FF6, length = 0x000002     /* Part of FLASHA.  Used for "boot to Flash" bootloader mode. */
       CSM_PWL_P0  : origin = 0x3F7FF8, length = 0x000008     /* Part of FLASHA.  CSM password locations in FLASHA */
    
       IQTABLES    : origin = 0x3FE000, length = 0x000B50     /* IQ Math Tables in Boot ROM */
       IQTABLES2   : origin = 0x3FEB50, length = 0x00008C     /* IQ Math Tables in Boot ROM */
       IQTABLES3   : origin = 0x3FEBDC, length = 0x0000AA	  /* IQ Math Tables in Boot ROM */
    
       ROM         : origin = 0x3FF27C, length = 0x000D44     /* Boot ROM */
       RESET       : origin = 0x3FFFC0, length = 0x000002     /* part of boot ROM  */
       VECTORS     : origin = 0x3FFFC2, length = 0x00003E     /* part of boot ROM  */
    
    PAGE 1 :   /* Data Memory */
               /* Memory (RAM/FLASH/OTP) blocks can be moved to PAGE0 for program allocation */
               /* Registers remain on PAGE1                                                  */
    
       RAMM0_M1    : origin = 0x000000, length = 0x000600     /* on-chip RAM block M0 + M1. 0x600 to 0x800 reserved for InstaSPIN */
       P_DRAML0    : origin = 0x008000, length = 0x001000     /* on-chip PRAM and DRAM blocks L0 */
       FLASHA_B    : origin = 0x3F4000, length = 0x003F80     /* on-chip FLASH A and B */
    }
    
    /* Allocate sections to memory blocks.
       Note:
             codestart user defined section in DSP28_CodeStartBranch.asm used to redirect code
                       execution when booting to flash
             ramfuncs  user defined section to store functions that will be copied from Flash into RAM
    */
    
    SECTIONS
    {
       /* Allocate program areas: */
       .cinit              : > FLASHA_B     PAGE = 1
       .pinit              : > FLASHA_B,    PAGE = 1
       .text               : > FLASHA_B     PAGE = 1
       codestart           : > BEGIN        PAGE = 0
       ramfuncs            : LOAD = FLASHA_B,
                             RUN = P_DRAML0,
                             LOAD_START(_RamfuncsLoadStart),
                             LOAD_END(_RamfuncsLoadEnd),
                             RUN_START(_RamfuncsRunStart),
                             PAGE = 1
    
       csmpasswds          : > CSM_PWL_P0   PAGE = 0
       csm_rsvd            : > CSM_RSVD     PAGE = 0
    
       /* Allocate uninitalized data sections: */
       .stack              : > RAMM0_M1   PAGE = 1
       .ebss               : > RAMM0_M1   PAGE = 1
       .esysmem            : > RAMM0_M1   PAGE = 1
    
       /* Initalized sections go in Flash */
       /* For SDFlash to program these, they must be allocated to page 0 */
       .econst             : > FLASHA_B     PAGE = 1
       .switch             : > FLASHA_B     PAGE = 1
    
       /* Allocate IQ math areas: */
       IQmath              : > FLASHA_B     PAGE = 1            /* Math Code */
       IQmathTables        : > IQTABLES,    PAGE = 0, TYPE = NOLOAD
    
       /* Uncomment the section below if calling the IQNexp() or IQexp()
          functions from the IQMath.lib library in order to utilize the
          relevant IQ Math table in Boot ROM (This saves space and Boot ROM
          is 1 wait-state). If this section is not uncommented, IQmathTables2
          will be loaded into other memory (SARAM, Flash, etc.) and will take
          up space, but 0 wait-state is possible.
       */
       /*
       IQmathTables2    : > IQTABLES2, PAGE = 0, TYPE = NOLOAD
       {
    
                  IQmath.lib<IQNexpTable.obj> (IQmathTablesRam)
    
       }
       */
       /* Uncomment the section below if calling the IQNasin() or IQasin()
          functions from the IQMath.lib library in order to utilize the
          relevant IQ Math table in Boot ROM (This saves space and Boot ROM
          is 1 wait-state). If this section is not uncommented, IQmathTables2
          will be loaded into other memory (SARAM, Flash, etc.) and will take
          up space, but 0 wait-state is possible.
       */
       /*
       IQmathTables3    : > IQTABLES3, PAGE = 0, TYPE = NOLOAD
       {
    
                  IQmath.lib<IQNasinTable.obj> (IQmathTablesRam)
    
       }
       */
    
       /* .reset is a standard section used by the compiler.  It contains the */
       /* the address of the start of _c_int00 for C Code.   /*
       /* When using the boot ROM this section and the CPU vector */
       /* table is not needed.  Thus the default type is set here to  */
       /* DSECT  */
       .reset              : > RESET,      PAGE = 0, TYPE = DSECT
       vectors             : > VECTORS     PAGE = 0, TYPE = DSECT
    
    }
    
    /*
    //===========================================================================
    // End of file.
    //===========================================================================
    */
    
    
    /*
    // TI File $Revision: /main/7 $
    // Checkin $Date: July 6, 2009   17:25:36 $
    //###########################################################################
    //
    // FILE:	F28027.cmd
    //
    // TITLE:	Linker Command File For F28027 Device
    //
    //###########################################################################
    // $TI Release: 2802x C/C++ Header Files and Peripheral Examples V1.29 $
    // $Release Date: January 11, 2011 $
    //###########################################################################
    */
    
    /* ======================================================
    // For Code Composer Studio V2.2 and later
    // ---------------------------------------
    // In addition to this memory linker command file,
    // add the header linker command file directly to the project.
    // The header linker command file is required to link the
    // peripheral structures to the proper locations within
    // the memory map.
    //
    // The header linker files are found in <base>\DSP2802_Headers\cmd
    //
    // For BIOS applications add:      DSP2802x_Headers_BIOS.cmd
    // For nonBIOS applications add:   DSP2802x_Headers_nonBIOS.cmd
    ========================================================= */
    
    /* ======================================================
    // For Code Composer Studio prior to V2.2
    // --------------------------------------
    // 1) Use one of the following -l statements to include the
    // header linker command file in the project. The header linker
    // file is required to link the peripheral structures to the proper
    // locations within the memory map                                    */
    
    /* Uncomment this line to include file only for non-BIOS applications */
    /* -l DSP2802x_Headers_nonBIOS.cmd */
    
    /* Uncomment this line to include file only for BIOS applications */
    /* -l DSP2802x_Headers_BIOS.cmd */
    
    /* 2) In your project add the path to <base>\DSP2802x_headers\cmd to the
       library search path under project->build options, linker tab,
       library search path (-i).
    /*========================================================= */
    
    /* Define the memory block start/length for the F28027
       PAGE 0 will be used to organize program sections
       PAGE 1 will be used to organize data sections
    
       Notes:
             Memory blocks on F2802x are uniform (ie same
             physical memory) in both PAGE 0 and PAGE 1.
             That is the same memory region should not be
             defined for both PAGE 0 and PAGE 1.
             Doing so will result in corruption of program
             and/or data.
    
             The L0 memory block is mirrored - that is
             it can be accessed in high memory or low memory.
             For simplicity only one instance is used in this
             linker file.
    
             Contiguous SARAM memory blocks or flash sectors can be
             be combined if required to create a larger memory block.
    */
    
    MEMORY
    {
    PAGE 0:    /* Program Memory */
               /* Memory (RAM/FLASH/OTP) blocks can be moved to PAGE1 for data allocation */
    
       OTP         : origin = 0x3D7800, length = 0x000400     /* on-chip OTP */
       CSM_RSVD    : origin = 0x3F7F80, length = 0x000076     /* Part of FLASHA.  Program with all 0x0000 when CSM is in use. */
       BEGIN       : origin = 0x3F7FF6, length = 0x000002     /* Part of FLASHA.  Used for "boot to Flash" bootloader mode. */
       CSM_PWL_P0  : origin = 0x3F7FF8, length = 0x000008     /* Part of FLASHA.  CSM password locations in FLASHA */
    
       IQTABLES    : origin = 0x3FE000, length = 0x000B50     /* IQ Math Tables in Boot ROM */
       IQTABLES2   : origin = 0x3FEB50, length = 0x00008C     /* IQ Math Tables in Boot ROM */
       IQTABLES3   : origin = 0x3FEBDC, length = 0x0000AA	  /* IQ Math Tables in Boot ROM */
    
       ROM         : origin = 0x3FF27C, length = 0x000D44     /* Boot ROM */
       RESET       : origin = 0x3FFFC0, length = 0x000002     /* part of boot ROM  */
       VECTORS     : origin = 0x3FFFC2, length = 0x00003E     /* part of boot ROM  */
    
    PAGE 1 :   /* Data Memory */
               /* Memory (RAM/FLASH/OTP) blocks can be moved to PAGE0 for program allocation */
               /* Registers remain on PAGE1                                                  */
    
       RAMM0_M1    : origin = 0x000000, length = 0x000600     /* on-chip RAM block M0 + M1. 0x600 to 0x800 reserved for InstaSPIN */
       P_DRAML0    : origin = 0x008000, length = 0x001000     /* on-chip PRAM and DRAM blocks L0 */
       FLASHA_D    : origin = 0x3F0000, length = 0x007F80     /* on-chip FLASH A, B, C and D */
    }
    
    /* Allocate sections to memory blocks.
       Note:
             codestart user defined section in DSP28_CodeStartBranch.asm used to redirect code
                       execution when booting to flash
             ramfuncs  user defined section to store functions that will be copied from Flash into RAM
    */
    
    SECTIONS
    {
       /* Allocate program areas: */
       .cinit              : > FLASHA_D     PAGE = 1
       .pinit              : > FLASHA_D,    PAGE = 1
       .text               : > FLASHA_D     PAGE = 1
       codestart           : > BEGIN        PAGE = 0
       ramfuncs            : LOAD = FLASHA_D,
                             RUN = P_DRAML0,
                             LOAD_START(_RamfuncsLoadStart),
                             LOAD_END(_RamfuncsLoadEnd),
                             RUN_START(_RamfuncsRunStart),
                             PAGE = 1
    
       csmpasswds          : > CSM_PWL_P0   PAGE = 0
       csm_rsvd            : > CSM_RSVD     PAGE = 0
    
       /* Allocate uninitalized data sections: */
       .stack              : > RAMM0_M1   PAGE = 1
       .ebss               : > RAMM0_M1   PAGE = 1
       .esysmem            : > RAMM0_M1   PAGE = 1
    
       /* Initalized sections go in Flash */
       /* For SDFlash to program these, they must be allocated to page 0 */
       .econst             : > FLASHA_D     PAGE = 1
       .switch             : > FLASHA_D     PAGE = 1
    
       /* Allocate IQ math areas: */
       IQmath              : > FLASHA_D     PAGE = 1            /* Math Code */
       IQmathTables        : > IQTABLES,    PAGE = 0, TYPE = NOLOAD
    
       /* Uncomment the section below if calling the IQNexp() or IQexp()
          functions from the IQMath.lib library in order to utilize the
          relevant IQ Math table in Boot ROM (This saves space and Boot ROM
          is 1 wait-state). If this section is not uncommented, IQmathTables2
          will be loaded into other memory (SARAM, Flash, etc.) and will take
          up space, but 0 wait-state is possible.
       */
       /*
       IQmathTables2    : > IQTABLES2, PAGE = 0, TYPE = NOLOAD
       {
    
                  IQmath.lib<IQNexpTable.obj> (IQmathTablesRam)
    
       }
       */
       /* Uncomment the section below if calling the IQNasin() or IQasin()
          functions from the IQMath.lib library in order to utilize the
          relevant IQ Math table in Boot ROM (This saves space and Boot ROM
          is 1 wait-state). If this section is not uncommented, IQmathTables2
          will be loaded into other memory (SARAM, Flash, etc.) and will take
          up space, but 0 wait-state is possible.
       */
       /*
       IQmathTables3    : > IQTABLES3, PAGE = 0, TYPE = NOLOAD
       {
    
                  IQmath.lib<IQNasinTable.obj> (IQmathTablesRam)
    
       }
       */
    
       /* .reset is a standard section used by the compiler.  It contains the */
       /* the address of the start of _c_int00 for C Code.   /*
       /* When using the boot ROM this section and the CPU vector */
       /* table is not needed.  Thus the default type is set here to  */
       /* DSECT  */
       .reset              : > RESET,      PAGE = 0, TYPE = DSECT
       vectors             : > VECTORS     PAGE = 0, TYPE = DSECT
    
    }
    
    /*
    //===========================================================================
    // End of file.
    //===========================================================================
    */
    
    

  • obviously drop the .txt from the filename
  • Thanks for confirming.

    Just so people know the bad linker command gave me the following error when I tried to program the 28027.

    C28xx: Flash Programmer: Error encountered when writing to flash memory
  • Hi, I just found this thread after having spent many hours trying to find out why my project failed to load. At some point I was starting to think about depletion, though I am working with a few days old Launchpad.

    This is a significant problem and can get people stuck for good, because the error message does not give any hints. I think there should be an update ASAP (maybe through CCS?) or at least an email sent to everyone who has downloaded MotorWare 14 about it. At the very least, a link to this thread should be posted in the MW14 thread and every thread about F28027F flashing problems.

    Best,

    Giannis

  • I'll post in the MW 14 thread, good idea.  It will be updated in version 15 set for release late this summer.