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DMA chip select behavior on XINTF

Mark Fiedler
Prodigy 120 points

I have configured my DMA on the F28334 to do an 8-word burst read on XINTF zone 6.

Since this is all done as a single burst, I would expect the chip select to be asserted for the duration of the burst.

However, the chip select line is cycled between each word of the burst.  Is this correct behavior?  Is there a configuration somewhere that I am missing?

 

Thanks

  • 0
    TI__Guru* 93800 points

    Mark Fiedler said:

    I have configured my DMA on the F28334 to do an 8-word burst read on XINTF zone 6.

    Since this is all done as a single burst, I would expect the chip select to be asserted for the duration of the burst.

    However, the chip select line is cycled between each word of the burst.  Is this correct behavior?  Is there a configuration somewhere that I am missing?

    Mark,

    This may be due to the timing you've configured. 

    By design all XINTF accesses will begin on the rising edge of XCLKOUT.  If an access finishes on a falling edge of XCLKOUT then there will be an alignment cycle and during this time the chip select will go high.

    For example - if XCLKOUT = 1/2 XTIMCLK.   If the total access is an odd number of XTIMCLK cycles, the access will end on a falling edge of XCLKOUT and there will be an alignment cycle.

    If, instead, there is an even number of XTIMCLK cycles in the access, it will end on the rising edge of XCLKOUT and another access can immediately begin.

    Does this explain the behavior you are observing?

    -Lori

     

     

  • 0 in reply to Lori Heustess
    Prodigy 120 points

    I'm not sure if this applies to my situation or not.  Your explanation seems to imply that I should be able to adjust the timing by changing the XRDLEAD, XRDACTIVE, and XRDTRAIL parameters.  I have tried several combinations of these paramaters, but I still always see XZCS6 going high between each word of the burst. 

    Is it actually possible to have a DMA burst where the chip select line stays asserted for the entire burst?  On other processors I have worked with, this has always been the case.  I can't seem to find a timing diagram in any of the TI documentation for the DMA or XINTF that shows a multiword burst operation on XINTF.

  • 0 in reply to Mark Fiedler
    TI__Guru* 93800 points

    Mark,

    I checked with someone more familiar with the DMA.  

    What I said is true for back-to-back reads on the XINTF.  The key is the  DMA will not issue a read on each cycle.  It is copying data so it will issue a ead then write then read etc..  Minimum transfer time is 4 SYSCLKOUT cycles.

    -Lori

     

  • 0 in reply to Lori Heustess
    Prodigy 120 points

    I understand that, but it's not really the main point of my question.

    I'm interested in the behavior of the XZCS6 line during on a DMA burst read to an external device on Zone 6. 

    It would be advantageous for our application if the chip selected were asserted continuously during the entire burst rather than being switched off and on after every word.  This would allow us to use the chip select line to keep the external device from doing other things during a DMA burst.  For all of the configurations that we have tried, the chip select toggles on every word rather than staying asserted for the entire burst.  Is there any way to change this behavior on the XINTF?

  • 0 in reply to Mark Fiedler
    TI__Guru* 93800 points

    Mark Fiedler said:

    I'm interested in the behavior of the XZCS6 line during on a DMA burst read to an external device on Zone 6. 

    It would be advantageous for our application if the chip selected were asserted continuously during the entire burst rather than being switched off and on after every word.  This would allow us to use the chip select line to keep the external device from doing other things during a DMA burst.  For all of the configurations that we have tried, the chip select toggles on every word rather than staying asserted for the entire burst.  Is there any way to change this behavior on the XINTF?

    Mark,

    The chip select signal will only stay low if the reads are back-to-back (i.e. a new read is pending as the current read completes) .  Since there is a delay between the reads by the DMA the chip select signal will go high between the reads.

    -Lori

     

  • 0 in reply to Lori Heustess
    Prodigy 120 points

    Ok, understood - DMA won't keep the chip select low.

    Is it possible to get back-to-back reads on the F28334 XINTF without using DMA?  If so, how would that be accomplished.

  • 0 in reply to Mark Fiedler
    TI__Guru* 93800 points

    Mark Fiedler said:
    Is it possible to get back-to-back reads on the F28334 XINTF without using DMA?  If so, how would that be accomplished.

    Yes, with the CPU

    For writes, turn on the write buffer and do multiple writes to XINTF.  The write won't stall the CPU unless the buffer is full so for this case it is easy to get back-to-back accesses.

    For reads, the CPU will be stalled until the read completes - so if there is anything else besides read generated by the code segment it may not endup back-to-back.  The surest way would be an assembly routine.  In this case multiple MOVL or  RPT || PREAD or PWRITE instructions would do the trick.

    May I ask the application and restraints you have for chip select staying low?  I ask because we also get the opposite request where customers want the chip select to always go high between any two accesses.

    Regards,

    Lori

  • 0 in reply to Lori Heustess
    Prodigy 120 points

    Our external device is an FPGA.  There are a set of registers on the FPGA that we want to read as a latched group.  It would be convenient if we could use the chip select to signal the FPGA to latch the registers during the DMA transaction.