How to start ADC simultaneously form an external trigger (F28337D )?

Hi Louis,

Ok, first the simultaneous part:

Each ADC SOC has the following three configurations: ACQPS, trigger, and channel select.  If we look at the following example in ControlSUITE: C:\ti\controlSUITE\device_support\F2837xD\v150\F2837xD_examples_Cpu1\adc_soc_epwm\cpu01.  You will see these lines of code:

AdcaRegs.ADCSOC0CTL.bit.CHSEL = channel; //SOC0 will convert pin A0
AdcaRegs.ADCSOC0CTL.bit.ACQPS = acqps; //sample window is 100 SYSCLK cycles
AdcaRegs.ADCSOC0CTL.bit.TRIGSEL = 5; //trigger on ePWM1 SOCA/C

Which are setting up SOC0 on ADCA.  To get simultaneous operation, just setup two SOCs on two ADCs with identical trigger and ACPQS values:

AdcaRegs.ADCSOC0CTL.bit.CHSEL = 0; //SOC0 will convert pin A0 (12-bit mode) or A0/A1 (16-bit mode).
AdcaRegs.ADCSOC0CTL.bit.ACQPS = acqps; //sample window is 100 SYSCLK cycles
AdcaRegs.ADCSOC0CTL.bit.TRIGSEL = 5; //trigger on ePWM1 SOCA/C

AdcbRegs.ADCSOC0CTL.bit.CHSEL = 2; //SOC0 will convert pin B2 or B2/B3.
AdcbRegs.ADCSOC0CTL.bit.ACQPS = acqps; //sample window is 100 SYSCLK cycles
AdcbRegs.ADCSOC0CTL.bit.TRIGSEL = 5; //trigger on ePWM1 SOCA/C

As long as there aren't other SOCs configured on one ADC that aren't configured on the other, the ADCs will operate synchronously.  As far as 16-bit mode, this is a global setting in each ADC module (it affects all the conversions for that ADC), so you will want to set both ADCs to 16-bit, differential mode.  Note that the channel settings can be different, depending on what channels you want to convert simultaneously (can be any channels from each of the ADCs). Also note that 16-bit channels are differential, so it is actually a pair of channels.

The above snippet will trigger on ePWM1 SOCA event.  You can change this to something else by chaning '5' in both configurations to something else (including the value for external pin XINT2).  I am not sure if this is what you want though. Can you clarify a little bit on exactly what you want to happen with the comparator triggering the ePWM?  If the threshold is crossed, do you want the trigger to the ADC to be delayed between 2^6 and 2^10 cycles?  What determines the length of these cycles (is it SYSCLK, a divided down SYSCLK, or some other asynchronous clock?).

Hi Devin,

Thanks for the reply. This will help me getting started.

Excuse me if my question was not clear. This is a special FFT application. The sampling must be in sync with the frequency of the input signal. For example if the input signal frequency is 100Hz and we need 1024-point FFT then we need to set the sampling frequency to 100 * 1024 = 102.400 kHz. This is necessary to avoid the “spectral leakage” of FFT (which happens when we do not have integer periods of the input signal sampled).

We have two input channels. (Same frequency but different phase). The INPUT_A channel will be connected to ADCA.Channel0-1 and the INPUT_B channel to ADCB.channel0-1. The INPUT_A channel also will be connected to COMPA comparator's + input, the VREF/2 to COMPA - input. The COMPA should be configured to change the output at every rising edge. The COMPA output is connected:

1. To the input of the external (?) PLL which multiplies it with 1024 (2^N). This is the sampling signal of ADCA and ADCB.
2. To the channel 1 of the eCAPx to measure the period time of the input signal.

So what do you think?
Best regards,
Louis

Hi Louis,
I am not sure that it will be possible to have the sampling frequency be fully coherent with the input signal if the input signal frequency is changing. The sampling frequency eventually must be an integer multiple of the SYSCLK (even if an external triggering signal is syncronized with the input signal, the samples still end up syncronous with SYSCLK). The preferred way to limit the spectral leakage would probably be to use a windowing function. I think you would still want to use the comparator -> eCAP to continuously measure the input signal frequency, and adjust the sampling frequency as needed to be in the ballpark of the desired number of input cycles per record.

Hi Devin,

This PLL based system works (since 2003) with a Silicon Labs 8051F120 and 8051F060 8-bit CPUs just fine. Now we need to simplify the design and move to the 32-bit CPU platform using the latest technologies.

What I wonder originally was how can I configure a GPIO (and which one) to start the ADCA and ADCB at the same time form a single MCU pin? It would be nice if the MCU would contain a low frequency PLL but the internal PLL(s) can only be used for generating SYSCLK.

Best regards,
Louis

Hi Devin,

Excellent, this is what I needed. Your idea about the „software PLL” is amazing good. Many thanks for your help!!!

Best regards,
Louis