SPI Communication with FPGA

Akshay SHah

I am using F28M35 Concerto which is communicating with FPGA on SPI bus(4- wire)(Mode 0). Can you tell me the maximum frequency at which full duplex communication can be done ? I have set LSPCLK to 75 MHz. At this case I am receiving data in my fpga correctly ( @ 18.75MHz which is maximum possible SPICLK in this case ) but Concerto misses one bit. I am little bit of confusede why it is happening. What is the maximum frequency at which Concerto can receive and transmits the data to any device on SPI slave ? Waiting reply urgently !

Regards,

Akshay

over 10 years ago

0 Gaston_Melo_Arg over 10 years ago

Mastermind 7675 points

Akshay,

check the errata for possibles issues

Regards

Gastón

0 Akshay SHah over 10 years ago in reply to Gaston_Melo_Arg

Prodigy 30 points

Dear Gaston,

First of all thanks very much for urgent reply !
As you have suggested in errata I have not found anything about spiclk ! Do you have any information about max clk that can be used as max spi clk frequency at which I can communicate both way !

Regards,
Akshay

0 Gautam Iyer over 10 years ago in reply to Akshay SHah

Guru 192875 points

Hi Akshay,

Do you have any information about max clk that can be used as max spi clk frequency at which I can communicate both way !

Its LSPCLK/4. Did you try with a lower SPICLK ie less than 18.75MHz?

Regards,
Gautam

0 Akshay SHah over 10 years ago in reply to Gautam Iyer

Prodigy 30 points

Hi Gautam,

I have checked @18.75 MHz and at lower frequency. All bits that are transmitted by dsp is correctly received in my fpga. But I am facing some problem at receiver side. Data is changing correctly at every edges but dsp can not latch it correctly ! I am attaching waveform of the same.

I have sent 1234H from my fpga.

In waveform CH2: SCLK

CH1: DATA coming from FPGA

But at UART can not able to receive correct data.

Regards,

Akshay

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SPI Communication with FPGA