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Question about Pulldown of GPIO in F28335

Slava Evseev
Prodigy 40 points
Other Parts Discussed in Thread: SN74ACT244

Hello!

All GPIO PINS in F28335 (but not gpio0-11 (EPWM)) have an internal pullup if XRSn line is low (and after reset). In my application i need that some GPIO lines have a low level during reset (these GPIO pins connect to input of SN74ACT244). I want to use the external pulldown resistor 3.3 kohm. Value of 3.3 kohm of pulldown resistor if sufficient to drive the gpio line to low level or not?

P.S. Epwm pins are used in this application for other purposes.

Sorry for my english.

  • 0
    TI__Guru 61235 points

    Hello Slava,

    Reference the device datasheet SPRS439m, section 6.3.  With the internal pullup enabled, the device will source 190 uA max trying to keep the pin high.  Using V=iR, you will get a (3.3K)*(190 uA) = 0.63 V rise from ground across your 3.3K pulldown.  The SN74ACT244 datasheet SCAS517C p.3 shows 0.8V max for logic low on the SN74ACT244.  Although 0.63V is below 0.8V, it is getting kind of close for reliable determination.  You get a little noise on the pin, and it could get mis-interpreted.  I'd be more comfortable if you used a 2.2K pulldown.

    Regards,

    David