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TMS320F28075 Immediate Watchdog Reset Clears Memory

Stefan W
Intellectual 280 points


Hi,

we are forcing an immediate watchdog reset on the F28075 from software by writing to the WDCR register with all zeros (WDCHK != 101). This works fine in the first sight, but it seems that this action clears all the RAM between 0x8000 and 0x14000. M0 and M1 stays the same.

Is this what it is expected to do? Or am I doing something wrong?

Thanks and best regards,

Stefan W.

  • 0
    TI__Guru** 116021 points

    Hi Stefan,

    Any reset which toggles XRSn pin will clear the RAMs on this device. WD reset is one of such reset hence it'll clear all the RAMs. Are you sure that content of M0/M1 stays the same? Could you double check on this?

    Regards,

    Vivek Singh

  • 0 in reply to Vivek Singh
    Intellectual 280 points

    Hi Vivek,

    I think you could be right. It was the debugger that bluffed me. After writing to WDCHK the memory from 0x8000 to 0x14000 was immediately cleared and could not be written anymore, but the M0 and M1 area was cleared after the controller performed the reset.

    Is really all the RAM cleared? Are there any free-to-use registers or RAM areas that are not cleared? Can we perform another kind of software reset that does not toggle XRSn?

    Thanks and best regards,

    Stefan W.

  • 0 in reply to Stefan W
    TI__Guru** 116021 points

    Hi Stefan,

    Yes, all the RAMs are cleared on any RESET which toggles XRSn pins. This is done to initialize the ECC/Parity value properly.

    Are there any free-to-use registers or RAM areas that are not cleared?

    This post has detail on this https://e2e.ti.com/support/microcontrollers/c2000/f/171/t/424691

    Let me know if you have any further questions.

    Regards,

    Vivek Singh

  • 0 in reply to Vivek Singh
    Intellectual 280 points

    Hi Vivek,

    you have written that there are for example these two registers (HIBBOOTMODE and ORESTOREADDR). Are there anymore? Where can I find information about which registers are not cleared via XRSn-Reset? I could not find anything about that in the TRM.

    Otherwise we will try to reduce the data to retain when performing a reset, so that it will fit into 54bit. We have migrated our code from 28069 and it is a pity that the RAM INIT "feature" turned out to be a stumbling block for us.

    Thanks and best regards,

    Stefan W.

  • 0 in reply to Stefan W
    TI__Guru** 116021 points

    Hi Stefan,

    There are other registers (very few though) but those are functional and used in all the modes so we don't recommend users to use them. Even these register (HIBBOOTMODE and ORESTOREADDR) can be used only if user is not using the HIBERNATE MODE of device.

    Please note that memories on F28069 didn't have ECC//Parity feature. This is new on this device hence this change in BOOT process. Still, I understand your concern with this issue and I'll communicate this to team to see how this can be resolved on our next device.  

    If you cannot reduce the data size then you could store it in a Flash sector before issuing WD reset (if you have SW control over this reset). If WD reset is happening due to some system failure then this may not be done.

    Regards,

    Vivek Singh 

  • 0 in reply to Vivek Singh
    Genius 4087 points

    I support Stefans request for RAM regions NOT being cleared by a reset. We are also migrating from 28069 and really used the RAM "feature" not being changed by a watchdog reset for signalling reset causes, events startup conditions,...
    Doing this in flash on the 2807x is not an option - it would wear out any flash when done on every reset.


    Regards,

    Stephan

  • 0 in reply to StephanS
    TI__Guru** 116021 points

    Hi Stephan,

    This device has RESC register which indicate which event has caused reset (including WD/NMI WD). There are other status registers also which indicate error conditions (NMI source). These are new status register on this device to help debug. There are also some registers which doesn't get reset by WD reset and can be used to store some debug info.

    As mentioned earlier, we have taken this feedback for next device.

    Regards,

    Vivek Singh