F28377d running from flash standalone

What do you mean it does not run the hysteresis control part? What do you mean the code is partially running?

Are you using both CPU1 and CPU2? What CPU is doing what?

sal

Hello Sal,
Thank you for your reply.
All the code is in CPU1. By not running, I mean the PWM signal that would be generated in the debug mode is not there when I run it standalone. The link I mentioned in the last post suggest that I do a FLASH to RAM copy at the very beginning of the code, I did that, still the same problem. I am not 100% sure I did the FLASH to RAM copy correctly though.

So what I did for the copy (following app note spraau8) :
1, I change CodeStartBranch.asm to the following:
***********************************************************************

WD_DISABLE .set 1 ;set to 1 to disable WD, else set to 0

.ref copy_sections
.global code_start

***********************************************************************
* Function: codestart section
*
* Description: Branch to code starting point
***********************************************************************

.sect "codestart"

code_start:
.if WD_DISABLE == 1
LB wd_disable ;Branch to watchdog disable code
.else
LB copy_sections ;Branch to copy_sections
.endif

;end codestart section

***********************************************************************
* Function: wd_disable
*
* Description: Disables the watchdog timer
***********************************************************************
.if WD_DISABLE == 1

.sect "wddisable"
.text
wd_disable:
SETC OBJMODE ;Set OBJMODE for 28x object code
EALLOW ;Enable EALLOW protected register access
MOVZ DP, #7029h>>6 ;Set data page for WDCR register
MOV @7029h, #0068h ;Set WDDIS bit in WDCR to disable WD
EDIS ;Disable EALLOW protected register access
LB copy_sections ;Branch to copy_sections

.endif

;end wd_disable

.end

2, add a another .asm in the project like this:


.ref _c_int00
.global copy_sections
.global _cinit_loadstart, _cinit_runstart, _cinit_size
.global _econst_loadstart, _econst_runstart, _econst_size
.global _pinit_loadstart, _pinit_runstart, _pinit_size
.global _switch_loadstart, _switch_runstart, _switch_size
.global _text_loadstart, _text_runstart, _text_size

***********************************************************************
* Function: copy_sections
*
* Description: Copies initialized sections from flash to ram
***********************************************************************

.sect "copysections"

copy_sections:

MOVL XAR5,#_econst_size ; Store Section Size in XAR5
MOVL ACC,@XAR5 ; Move Section Size to ACC
MOVL XAR6,#_econst_loadstart ; Store Load Starting Address in XAR6
MOVL XAR7,#_econst_runstart ; Store Run Address in XAR7
LCR copy ; Branch to Copy

MOVL XAR5,#_pinit_size ; Store Section Size in XAR5
MOVL ACC,@XAR5 ; Move Section Size to ACC
MOVL XAR6,#_pinit_loadstart ; Store Load Starting Address in XAR6
MOVL XAR7,#_pinit_runstart ; Store Run Address in XAR7
LCR copy ; Branch to Copy

MOVL XAR5,#_switch_size ; Store Section Size in XAR5
MOVL ACC,@XAR5 ; Move Section Size to ACC
MOVL XAR6,#_switch_loadstart ; Store Load Starting Address in XAR6
MOVL XAR7,#_switch_runstart ; Store Run Address in XAR7
LCR copy ; Branch to Copy


MOVL XAR5,#_cinit_size ; Store Section Size in XAR5
MOVL ACC,@XAR5 ; Move Section Size to ACC
MOVL XAR6,#_cinit_loadstart ; Store Load Starting Address in XAR6
MOVL XAR7,#_cinit_runstart ; Store Run Address in XAR7
LCR copy ; Branch to Copy

LB _c_int00 ; Branch to start of boot.asm in RTS library

copy:
B return,EQ ; Return if ACC is Zero (No section to copy)

RPT AL ; Copy Section From Load Address to
|| PWRITE *XAR7, *XAR6++ ; Run Address

return:
LRETR ; Return

.end

3, make .cmd linker file like this:
MEMORY
{
PAGE 0 : /* Program Memory */
/* Memory (RAM/FLASH) blocks can be moved to PAGE1 for data allocation */
/* BEGIN is used for the "boot to Flash" bootloader mode */

BEGIN : origin = 0x080000, length = 0x000002
RAMM0 : origin = 0x000122, length = 0x0002DE
RAMD0 : origin = 0x00B000, length = 0x000800
RAMLS0 : origin = 0x008000, length = 0x000800
RAMLS1 : origin = 0x008800, length = 0x000800
RAMLS2 : origin = 0x009000, length = 0x000800
RAMLS3 : origin = 0x009800, length = 0x000800
RAMLS4 : origin = 0x00A000, length = 0x000800
RESET : origin = 0x3FFFC0, length = 0x000002

/* Flash sectors */
FLASHA : origin = 0x080002, length = 0x001FFE /* on-chip Flash */
FLASHB : origin = 0x082000, length = 0x002000 /* on-chip Flash */
FLASHC : origin = 0x084000, length = 0x002000 /* on-chip Flash */
FLASHD : origin = 0x086000, length = 0x002000 /* on-chip Flash */
FLASHE : origin = 0x088000, length = 0x008000 /* on-chip Flash */
FLASHF : origin = 0x090000, length = 0x008000 /* on-chip Flash */
FLASHG : origin = 0x098000, length = 0x008000 /* on-chip Flash */
FLASHH : origin = 0x0A0000, length = 0x008000 /* on-chip Flash */
FLASHI : origin = 0x0A8000, length = 0x008000 /* on-chip Flash */
FLASHJ : origin = 0x0B0000, length = 0x008000 /* on-chip Flash */
FLASHK : origin = 0x0B8000, length = 0x002000 /* on-chip Flash */
FLASHL : origin = 0x0BA000, length = 0x002000 /* on-chip Flash */
FLASHM : origin = 0x0BC000, length = 0x002000 /* on-chip Flash */
FLASHN : origin = 0x0BE000, length = 0x002000 /* on-chip Flash */

PAGE 1 : /* Data Memory */
/* Memory (RAM/FLASH) blocks can be moved to PAGE0 for program allocation */

BOOT_RSVD : origin = 0x000002, length = 0x000120 /* Part of M0, BOOT rom will use this for stack */
RAMM1 : origin = 0x000400, length = 0x000400 /* on-chip RAM block M1 */
RAMD1 : origin = 0x00B800, length = 0x000800

RAMLS5 : origin = 0x00A800, length = 0x000800

RAMGS0 : origin = 0x00C000, length = 0x001000
RAMGS1 : origin = 0x00D000, length = 0x001000
RAMGS2 : origin = 0x00E000, length = 0x001000
RAMGS3 : origin = 0x00F000, length = 0x001000
RAMGS4 : origin = 0x010000, length = 0x001000
RAMGS5 : origin = 0x011000, length = 0x001000
RAMGS6 : origin = 0x012000, length = 0x001000
RAMGS7 : origin = 0x013000, length = 0x001000
RAMGS8 : origin = 0x014000, length = 0x001000
RAMGS9 : origin = 0x015000, length = 0x001000
RAMGS10 : origin = 0x016000, length = 0x001000
RAMGS11 : origin = 0x017000, length = 0x001000
RAMGS12 : origin = 0x018000, length = 0x001000
RAMGS13 : origin = 0x019000, length = 0x001000
RAMGS14 : origin = 0x01A000, length = 0x002000
// RAMGS15 : origin = 0x01B000, length = 0x001000


CPU2TOCPU1RAM : origin = 0x03F800, length = 0x000400
CPU1TOCPU2RAM : origin = 0x03FC00, length = 0x000400
}


SECTIONS
{
/* Allocate program areas: */
.cinit : LOAD = FLASHB, PAGE = 0, ALIGN(4)
RUN = RAMM0, PAGE = 0
LOAD_START(_cinit_loadstart),
RUN_START(_cinit_runstart),
SIZE(_cinit_size)

.pinit : LOAD = FLASHB, PAGE = 0, ALIGN(4)
RUN = RAMM0, PAGE = 0
LOAD_START(_pinit_loadstart),
RUN_START(_pinit_runstart),
SIZE(_pinit_size)

.text : >> FLASHB | FLASHC | FLASHD | FLASHE PAGE = 0, ALIGN(4)
// RUN = RAMM0 | RAMD0 | RAMLS0 | RAMLS1 | RAMLS2 | RAMLS3 | RAMLS4, PAGE = 0
// LOAD_START(_text_loadstart),
// RUN_START(_text_runstart),
// SIZE(_text_size)

codestart : > BEGIN PAGE = 0, ALIGN(4)
wddisable : > FLASHA PAGE = 0, ALIGN(4)
copysections : > FLASHA PAGE = 0, ALIGN(4)
ramfuncs : LOAD = FLASHD,
RUN = RAMLS0 | RAMLS1 | RAMLS2 |RAMLS3,
LOAD_START(_RamfuncsLoadStart),
LOAD_SIZE(_RamfuncsLoadSize),
LOAD_END(_RamfuncsLoadEnd),
RUN_START(_RamfuncsRunStart),
RUN_SIZE(_RamfuncsRunSize),
RUN_END(_RamfuncsRunEnd),
PAGE = 0, ALIGN(4)

/* Allocate uninitalized data sections: */
.stack : > RAMM1 PAGE = 1
.ebss : > RAMGS14 PAGE = 1
.esysmem : > RAMLS5 PAGE = 1

/* Initalized sections go in Flash */
.econst : LOAD = FLASHF | FLASHG | FLASHH PAGE = 0, ALIGN(4)
RUN = RAMLS5, PAGE = 1
LOAD_START(_econst_loadstart),
RUN_START(_econst_runstart),
SIZE(_econst_size)

.switch : LOAD = FLASHB PAGE = 0, ALIGN(4)
RUN = RAMM0, PAGE = 0
LOAD_START(_switch_loadstart),
RUN_START(_switch_runstart),
SIZE(_switch_size)

.reset : > RESET, PAGE = 0, TYPE = DSECT /* not used, */

Filter_RegsFile : > RAMGS0, PAGE = 1

SHARERAMGS0 : > RAMGS0, PAGE = 1
SHARERAMGS1 : > RAMGS1, PAGE = 1

/* The following section definitions are required when using the IPC API Drivers */
GROUP : > CPU1TOCPU2RAM, PAGE = 1
{
PUTBUFFER
PUTWRITEIDX
GETREADIDX
}

GROUP : > CPU2TOCPU1RAM, PAGE = 1
{
GETBUFFER : TYPE = DSECT
GETWRITEIDX : TYPE = DSECT
PUTREADIDX : TYPE = DSECT
}

}

These files can compiles and run.
Any direction would be greatly appreciated.
Thank you!

To get the code to run from RAM, you need to assign the function to the 'ramfuncs' section in the source file. Then you need to call memcpy.

memcpy(&RamfuncsRunStart, &RamfuncsLoadStart, (size_t)&RamfuncsLoadSize);

You can see examples in controlSUITE to see how to do this.
sal

Hello Sal,
Thank you for your reply.
How can I tell if the function is running from RAM or not? Is there a way to check?
Thank you!

Check out the disassembly window and see where the PC counter is. The PC counter tells you where the CPU is running.

sal

Hi Shibin Qin,

Did you succeed copying the code from FLASH to RAM ? I am also trying the same thing.

Hi Sal Pezzino,

I didn't understand what you mean by above code. Where is the 'ramfuncs' ? and
Where do I call "memcpy(&RamfuncsRunStart, &RamfuncsLoadStart, (size_t)&RamfuncsLoadSize);" exactly?

please consider looking at our controlSUITE examples. You can look at our flash programming examples.

sal

Hello, 

Yes, I follow the the app note and exactly the code in my previous post.. I am not 100% sure if it copy to RAM indeed, but it compiles fine and now it seems that my code runs just fine as well. 

Good to hear!