Hi.
I see from the technical reference manuals, that the size of the transmit/receive FIFO differs for e.g the 2806x (size is 4) or the 2807x (size is 16).
What we want to realize is to use the SCI in FIFO mode and to provide polled functions for reading or writing. However writing should fail (function should return a failure) if the TX FIFO is full. Sure we could define the size of the FIFO depending on the processor type but if there is a way to determine the buffer size in software it would be even better.
Is there a way to read the FIFO buffer size from any register?