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Receive data every 10Hz or so

Waqqas Khan
Prodigy 200 points

I am using ADC_SOC example as a base code. I am now trying to receive data from ADCin02 and ADCin03 at around 10Hz. Looking up in the ADC pdf file. I think I understand that I am looking at ADCCLK. ON page 26 of ADC pdf it says that to change ADCCLK, I have to turn on HISPCLK, ADCTRL3 and ADCTRL1. SYSCLKOUT is default 150 MHz. I turned on all bits, but the minimum ADCCLK I can get is around 150kHz. Can I take this number down to 10Hz. If yes, then how?

Thanks.

Waqqas

  • 0
    Guru 192875 points
    Hi Waqqas,

    Use CLKDIVs and configure an ePWM channel to trigger your ADC conversion.
    Here's the link that can direct you: e2e.ti.com/.../134703

    Regards,
    Gautam
  • 0
    TI__Guru 62975 points

    Waqqas,

    You might have better results by modifying the EPWM triggers to fire at 10Hz rather than slow down your ADC clocks to convert at 10Hz.

    This is because:

    1. As you slow down the ADC sample/conversion sequence, parasitic leakage may start to distort your conversions.
    2. Maintaining the ADC bandwidth allows you to insert additional ADC reads if you ever need to expand your application.

    -Tommy

  • 0 in reply to Gautam Iyer
    Prodigy 200 points
    Gautam,
    Thanks for the link. I looked over and understood the CLKDIVs. Attached below is the preliminary code using the example and the 2 lines that I added to make it 10Hz. I then ran the program. The receiving rate of data has slowed down. Though, I will look up on how to confirm that. My question is that is ADC_MODCLK doing in the basic code. Should I edit it or those 2 new lines are enough.


    EALLOW;
    #if (CPU_FRQ_150MHZ) // Default - 150 MHz SYSCLKOUT
    #define ADC_MODCLK 0x3 // HSPCLK = SYSCLKOUT/2*ADC_MODCLK2 = 150/(2*3) = 25.0 MHz
    #endif
    #if (CPU_FRQ_100MHZ)
    #define ADC_MODCLK 0x2 // HSPCLK = SYSCLKOUT/2*ADC_MODCLK2 = 100/(2*2) = 25.0 MHz
    #endif
    EDIS;
    EALLOW;
    SysCtrlRegs.HISPCP.all = ADC_MODCLK;
    .
    .
    .

    EPwm1Regs.TBCTL.bit.CLKDIV=0x3; ----------------------------------------------------------------NEW LINE
    EPwm1Regs.TBCTL.bit.HSPCLKDIV=0x7; ----------------------------------------------------------NEW LINE
    EPwm1Regs.ETSEL.bit.SOCAEN = 1; // Enable SOC on A group
    EPwm1Regs.ETSEL.bit.SOCASEL = 4; // Select SOC from from CPMA on upcount
    EPwm1Regs.ETPS.bit.SOCAPRD = 1; // Generate pulse on 1st event
    EPwm1Regs.CMPA.half.CMPA = 0x0080; // Set compare A value
    EPwm1Regs.TBPRD = 0xFFFF; // Set period for ePWM1
    EPwm1Regs.TBCTL.bit.CTRMODE = 10; // count up down and start

    Thanks
    Waqqas
  • 0 in reply to Waqqas Khan
    Guru 192875 points
    Yes, 2 CLKDIV should do the trick.