Problem With TMS320LF2407A Interrupts

Hi C Gent,

In C24xx family when you single step the interrupts are disabled (this is written somewhere in the TI docs) The one option I found as a workaround to your problem is to use command window and issue "run 1" command. This actually runs the DSP for one instruction, therefore the interrupts are enabled and you should observe proper procedure. Note this was tested only on old Code Composer 4.12 (NOT Code Composer Studio)

Regards, Mitja

Thank you for your reply

With Code Compser I can run with brake-points on the ISR and see when the timer ISR gets called

First thing in the morning, the ADC ISR will run until I reset the processor, then it will not call the isr again until I reboot the computer

I can reset the processor, power cycle, and restart code composer the ISR will not be called

I can see the timer ISR running & set brake points in it's entrance (allowing the processor to run until the brake-point)

it's not just a single step problem

(I also tried the "run 1" command as you suggested, it did not enter the ISR)

I need to get back to basics

What other registers should I be looking at?

I will be going over the config regs again today

Has anyone else seen a similar problem and what did you find ?

Moved the interrupts off of interrupt 1 to low priority interrupts

for the SCI and ADC , now they are working

Still an issue if you want to use int 1

Thanks for you help

Hi C Gent,

The symptoms you describe are very strange indeed. Before you proceed any further I would highly recommend that you stop and investigate why the system behaves in such way as it might (according to Murphy very likely) come back and manifest in slightly different way.

First thing I would do is switch back to high priority interrupts for ADC and SCI. Then I would set FREE and SOFT bits to 0 in ADCCTRL0 and observe the behavior of ADC, PIE and CPU flags when ADC finishes with conversion. The "run 1" instruction should be very helpful.

How is the ADC triggered?

Regards, Mitja

        /* Interrupt Mask Register */      
    IMR=((INT6<<5)+(INT5<<4)+(INT4<<3)+(INT3<<2)+(INT2<<1)+(INT1));

/****************************************************************/
/* Init ADC module for conversions*/
/****************************************************************/

    ADCCTRL1 =     0x4000;    //0100 0000 0000 0000b;     // Reset ADC module
    asm ("    NOP");                            // Needed after reset
    ADCCTRL1 =     0x3010;    //0011 0000 0001 0000b;     // Take ADC out of reset

// Setup a maximum of 16 conversions
    MAXCONV =     15;        // Setup for 16 conversions
// Program the conversion sequence. This is the sequence of channels that will
// be used for the 16 conversions.
    CHSELSEQ1 = 0x03210;         // Convert Channels 0,1,2,3
    CHSELSEQ2 = 0x07654;          // Convert Channels 4,5,6,7
    CHSELSEQ3 = 0x0BA98;          // Convert Channels 8,9,10,11
    CHSELSEQ4 = 0x0FEDC;          // Convert Channels 12,13,14,15
    ADCCTRL2  = 0x00200;         // clear interrupt bit
    ADCCTRL2  = 0x00400;         // enable interrupt

    IMR |= 0x002;
    asm(" EINT");           // Enable Global interrupt INTM
    ADCCTRL2 |= 0x2000;        /* start the converter*/

// in Main loop to restart the converter, about once every 0.5 sec

    if (!(ADCCTRL2 && 0x01010))
    {
        ADCCTRL2 |= 0x2000;    /* Restart the converter*/
    }   


// Interrupt routine
void c_int1(void)
    {
    switch(PIVR)   
    {
        case 0x04:                    //  0x04 ADC Interrupt (HI priority)
        {
            ADC_ISR();
             ADCCTRL2 |= 0x0200;            /* Clear flag*/
             break;
        }

When I started the computer cold the Processor entered the ISR multiple times, with break point on the int 1 memory location

after reset the processor did not jump to the int1 location. Above is snippets of the code, the registers are as above in first post

It has been a while since I've worked with C24xx family, bot from my code I've seen that during the initialization I've cleared all pending interrupts

"SPLK    #0000000000000000b,PIRQR0"  the same for PIRQR1 and 2 and I also clear all IFR flags "SPLK    #00111111b,IFR"

I don't have any comment why I've done this (here is clear example why it is good to write comments) but you might try it.

Do you by any chance use RT-MON package?

Regards, Mitja

From SPRU357C Section 2.10

Note:
PIRQR0/1/2 and PIACKR0/1/2 are control registers internal to the PIE
module used for generating interrupts (INT1 − INT6) to the CPU. While
programming, these registers can be ignored since they monitor the internal
operation of the PIE. These registers are used for test purposes and are not
intended for user applications.

I do clear the IFR  during initialization of the lf240, I had not clipped it into the above code snippet

(I added the clearing of the PIRQR0, 1, and 2 no change)

By the RT-MON package i assume you mean "C2000MNRT.asm" package from TI

Yes I have tried to get it to work but when it tries to access a variable it times out and gives an error

I have not tried to find out why yet.

Mitja, I do appreciate and thank you for your help with this problem

I've found the reason for tinkering with PIRQRx registers see errata regarding the "EV − PDPINTx Pin Operation"

Since we're in the blind spot, try changing the SCI interrupt to low priority while keeping the ADC in high priority and see what happens.

The other thing to test is to restart the PC, recompile the program with ADC and SCI interrupts in high priority and reset the CPU after the program is loaded. the CCS and GEL files are unchanged CCS puts the CPU to the beginning of C initialization code after the program is loaded. This is not necessarily the same point as the CPU reset points to. You might have some code that executes between CPU reset and C initialization that could cause these problems.

Regarding the RTMON I can only say that when you get it working it is very useful tool. but for now I would recommend to keep it disabled as it also tinkers with interrupt system.

Regards, Mitja