Other Parts Discussed in Thread: CONTROLSUITE
dear all,
I have written a small code & want it to run from flash. Please help.
Code:
//====================================================================================include file
#include "DSP28x_Project.h" // Device Headerfile and Examples Include File
#include <string.h>
#include <stdint.h>
//====================================================================================i/o definition
#define LCD_bit0 GpioDataRegs.GPADAT.bit.GPIO8
#define LCD_bit1 GpioDataRegs.GPADAT.bit.GPIO10
#define LCD_bit2 GpioDataRegs.GPADAT.bit.GPIO30
#define LCD_bit3 GpioDataRegs.GPBDAT.bit.GPIO32
#define LCD_bit4 GpioDataRegs.GPADAT.bit.GPIO9
#define LCD_bit5 GpioDataRegs.GPADAT.bit.GPIO11
#define LCD_bit6 GpioDataRegs.GPADAT.bit.GPIO31
#define LCD_bit7 GpioDataRegs.GPBDAT.bit.GPIO33
#define LCD_RS GpioDataRegs.GPADAT.bit.GPIO4
#define LCD_EN GpioDataRegs.GPADAT.bit.GPIO6
//====================================================================================value macro
#define line1_addr 0x80
#define line2_addr 0xc0
#define line3_addr 0x94
#define line4_addr 0xd4
#define end_char 13
//====================================================================================variable definition
unsigned char tho2,tho,hun,ten,one;
unsigned char lcd_port,temp,temp2;
//---------------------------------------------------------------------------
extern Uint16 RamfuncsLoadStart;
extern Uint16 RamfuncsLoadSize;
extern Uint16 RamfuncsRunStart;
//====================================================================================function definition
void LCDcmd (unsigned char);
void LCDtxt (unsigned char);
void LCDinit (void);
void snd_lcd_data(unsigned char);
void DELAY_MS(unsigned long);
void LCDstr (unsigned char *msg);
void LCDgoto(unsigned int,unsigned int);
void LCDclrline(unsigned int);
void LCDclr(void);
//======================================================================
void main(void)
{
InitSysCtrl();
EALLOW;
//-------------------------------------------------output
GpioCtrlRegs.GPADIR.bit.GPIO8=1;
GpioCtrlRegs.GPADIR.bit.GPIO10=1;
GpioCtrlRegs.GPADIR.bit.GPIO30=1;
GpioCtrlRegs.GPBDIR.bit.GPIO32=1;
GpioCtrlRegs.GPADIR.bit.GPIO9=1;
GpioCtrlRegs.GPADIR.bit.GPIO11=1;
GpioCtrlRegs.GPADIR.bit.GPIO31=1;
GpioCtrlRegs.GPBDIR.bit.GPIO33=1;
GpioCtrlRegs.GPADIR.bit.GPIO4=1;
GpioCtrlRegs.GPADIR.bit.GPIO6=1;
GpioCtrlRegs.GPAMUX1.bit.GPIO8=0;
GpioCtrlRegs.GPAMUX1.bit.GPIO10=0;
GpioCtrlRegs.GPAMUX2.bit.GPIO30=0;
GpioCtrlRegs.GPBMUX1.bit.GPIO32=0;
GpioCtrlRegs.GPAMUX1.bit.GPIO9=0;
GpioCtrlRegs.GPAMUX1.bit.GPIO11=0;
GpioCtrlRegs.GPAMUX2.bit.GPIO31=0;
GpioCtrlRegs.GPBMUX1.bit.GPIO33=0;
GpioCtrlRegs.GPAMUX1.bit.GPIO4=0;
GpioCtrlRegs.GPAMUX1.bit.GPIO6=0;
//-------------------------------------------------
EDIS;
DINT;
InitPieCtrl();
IER = 0x0000;
IFR = 0x0000;
InitPieVectTable();
memcpy((uint16_t *)&RamfuncsRunStart,(uint16_t *)&RamfuncsLoadStart, (unsigned long)&RamfuncsLoadSize);
InitFlash();
// Enable global Interrupts and higher priority real-time debug events:
EINT; // Enable Global interrupt INTM
ERTM; // Enable Global realtime interrupt DBGM
DELAY_MS(100);
//==================================================
LCDinit();
LCDgoto(1,0);
LCDstr (" WELD CONTROLLER v1 Ç");
while(1);
}
//---------------------------------------------Delay
void DELAY_MS(unsigned long t)
{
unsigned long i;
for (i=0;i<t;i++)
DELAY_US(1000);
}
////=====================================================LCD
void LCDclr(void){
LCDcmd(0x01);
DELAY_MS(100);
}
void LCDcmd (unsigned char cmd)
{ snd_lcd_data(cmd);
DELAY_MS(1);
LCD_RS=0;
DELAY_MS(1);
LCD_EN=1;
DELAY_MS(1);
LCD_EN=0;
DELAY_MS(1);
}
void LCDtxt (unsigned char txt)
{ snd_lcd_data(txt);
DELAY_MS(1);
LCD_RS=1;
DELAY_MS(1);
LCD_EN=1;
DELAY_MS(1);
LCD_EN=0;
DELAY_MS(1);
}
void LCDstr (unsigned char *msg){
while (*msg!='Ç')
LCDtxt(*msg++);
}
void LCDclrline(unsigned int col){
switch(col){
case 1:
LCDcmd(line1_addr);
break;
case 2:
LCDcmd(line2_addr);
break;
case 3:
LCDcmd(line3_addr);
break;
case 4:
LCDcmd(line4_addr);
break;
}
LCDstr(" Ç");
}
void LCDinit (void)
{
LCDcmd(0x30); // 4-bit mode - 2 line - 5x7 font.
DELAY_MS(20);
LCDcmd(0x30); // 4-bit mode - 2 line - 5x7 font.
DELAY_MS(1000);
LCDcmd(0x30); // 4-bit mode - 2 line - 5x7 font.
DELAY_MS(1000);
LCDcmd(0x38); // 4-bit mode - 2 line - 5x7 font.
DELAY_MS(20);
LCDcmd(0x38); // 4-bit mode - 2 line - 5x7 font.
DELAY_MS(20);
LCDcmd(0x38); // 4-bit mode - 2 line - 5x7 font.
DELAY_MS(20);
LCDcmd(0x0c); // Automatic Increment - No Display shift.
DELAY_MS(20);
LCDcmd(0x06); // 4-bit mode - 2 line - 5x7 font.
DELAY_MS(20);
LCDcmd(0x01); // Display no cursor - no blink.
DELAY_MS(20);
}
void LCDgoto(unsigned int row,unsigned int col){
switch(row){
case 1:
LCDcmd(line1_addr+col);
break;
case 2:
LCDcmd(line2_addr+col);
break;
case 3:
LCDcmd(line3_addr+col);
break;
case 4:
LCDcmd(line4_addr+col);
break;
}
}
void snd_lcd_data(unsigned char x)
{
temp=x;
if (temp & 0x80)
LCD_bit7=1;
else
LCD_bit7=0;
temp=x;
if (temp & 0x40)
LCD_bit6=1;
else
LCD_bit6=0;
temp=x;
if (temp & 0x20)
LCD_bit5=1;
else
LCD_bit5=0;
temp=x;
if (temp & 0x10)
LCD_bit4=1;
else
LCD_bit4=0;
temp=x;
if (temp & 0x08)
LCD_bit3=1;
else
LCD_bit3=0;
temp=x;
if (temp & 0x04)
LCD_bit2=1;
else
LCD_bit2=0;
temp=x;
if (temp & 0x02)
LCD_bit1=1;
else
LCD_bit1=0;
temp=x;
if ((temp & 0x01))
LCD_bit0=1;
else
LCD_bit0=0;
DELAY_US(10);
}
//---------------------------------------------------------
void LCD_buildchar(unsigned char location, unsigned char *ptr){
unsigned char i;
if(location<8){
LCDcmd(0x40+(location*8));
for(i=0;i<8;i++)
LCDtxt(ptr[ i ]);
}
}
F28035.cmd:
/*
// TI File $Revision: /main/4 $
// Checkin $Date: November 9, 2009 15:09:12 $
//###########################################################################
//
// FILE: F2808.cmd
//
// TITLE: Linker Command File For F2808 Device
//
//###########################################################################
// $TI Release: 2803x Internal Release 2 $
// $Release Date: November 11, 2008 $
//###########################################################################
*/
/* ======================================================
// For Code Composer Studio V2.2 and later
// ---------------------------------------
// In addition to this memory linker command file,
// add the header linker command file directly to the project.
// The header linker command file is required to link the
// peripheral structures to the proper locations within
// the memory map.
//
// The header linker files are found in <base>\DSP2803x_Headers\cmd
//
// For BIOS applications add: DSP2803x_Headers_BIOS.cmd
// For nonBIOS applications add: DSP2803x_Headers_nonBIOS.cmd
========================================================= */
/* ======================================================
// For Code Composer Studio prior to V2.2
// --------------------------------------
// 1) Use one of the following -l statements to include the
// header linker command file in the project. The header linker
// file is required to link the peripheral structures to the proper
// locations within the memory map */
/* Uncomment this line to include file only for non-BIOS applications */
/* -l DSP2803x_Headers_nonBIOS.cmd */
/* Uncomment this line to include file only for BIOS applications */
/* -l DSP2803x_Headers_BIOS.cmd */
/* 2) In your project add the path to <base>\DSP2803x_headers\cmd to the
library search path under project->build options, linker tab,
library search path (-i).
/*========================================================= */
/* Define the memory block start/length for the F28035
PAGE 0 will be used to organize program sections
PAGE 1 will be used to organize data sections
Notes:
Memory blocks on F2803x are uniform (ie same
physical memory) in both PAGE 0 and PAGE 1.
That is the same memory region should not be
defined for both PAGE 0 and PAGE 1.
Doing so will result in corruption of program
and/or data.
L0 memory block is mirrored - that is
it can be accessed in high memory or low memory.
For simplicity only one instance is used in this
linker file.
Contiguous SARAM memory blocks or flash sectors can be
be combined if required to create a larger memory block.
*/
MEMORY
{
PAGE 0: /* Program Memory */
/* Memory (RAM/FLASH/OTP) blocks can be moved to PAGE1 for data allocation */
RAML0 : origin = 0x008000, length = 0x000800 /* on-chip RAM block L0 */
RAML1 : origin = 0x008800, length = 0x000400 /* on-chip RAM block L1 */
OTP : origin = 0x3D7800, length = 0x000400 /* on-chip OTP */
FLASHH : origin = 0x3E8000, length = 0x002000 /* on-chip FLASH */
FLASHG : origin = 0x3EA000, length = 0x002000 /* on-chip FLASH */
FLASHF : origin = 0x3EC000, length = 0x002000 /* on-chip FLASH */
FLASHE : origin = 0x3EE000, length = 0x002000 /* on-chip FLASH */
FLASHD : origin = 0x3F0000, length = 0x002000 /* on-chip FLASH */
FLASHC : origin = 0x3F2000, length = 0x002000 /* on-chip FLASH */
FLASHA : origin = 0x3F6000, length = 0x001F80 /* on-chip FLASH */
CSM_RSVD : origin = 0x3F7F80, length = 0x000076 /* Part of FLASHA. Program with all 0x0000 when CSM is in use. */
BEGIN : origin = 0x3F7FF6, length = 0x000002 /* Part of FLASHA. Used for "boot to Flash" bootloader mode. */
CSM_PWL_P0 : origin = 0x3F7FF8, length = 0x000008 /* Part of FLASHA. CSM password locations in FLASHA */
IQTABLES : origin = 0x3FE000, length = 0x000B50 /* IQ Math Tables in Boot ROM */
IQTABLES2 : origin = 0x3FEB50, length = 0x00008C /* IQ Math Tables in Boot ROM */
IQTABLES3 : origin = 0x3FEBDC, length = 0x0000AA /* IQ Math Tables in Boot ROM */
ROM : origin = 0x3FF27C, length = 0x000D44 /* Boot ROM */
RESET : origin = 0x3FFFC0, length = 0x000002 /* part of boot ROM */
VECTORS : origin = 0x3FFFC2, length = 0x00003E /* part of boot ROM */
PAGE 1 : /* Data Memory */
/* Memory (RAM/FLASH/OTP) blocks can be moved to PAGE0 for program allocation */
/* Registers remain on PAGE1 */
BOOT_RSVD : origin = 0x000000, length = 0x000050 /* Part of M0, BOOT rom will use this for stack */
RAMM0 : origin = 0x000050, length = 0x0003B0 /* on-chip RAM block M0 */
RAMM1 : origin = 0x000400, length = 0x000400 /* on-chip RAM block M1 */
RAML2 : origin = 0x008C00, length = 0x000400 /* on-chip RAM block L2 */
RAML3 : origin = 0x009000, length = 0x001000 /* on-chip RAM block L3 */
FLASHB : origin = 0x3F4000, length = 0x002000 /* on-chip FLASH */
}
/* Allocate sections to memory blocks.
Note:
codestart user defined section in DSP28_CodeStartBranch.asm used to redirect code
execution when booting to flash
ramfuncs user defined section to store functions that will be copied from Flash into RAM
*/
SECTIONS
{
/* Allocate program areas: */
.cinit : > FLASHA PAGE = 0
.pinit : > FLASHA PAGE = 0
.text : > FLASHA PAGE = 0
codestart : > BEGIN PAGE = 0
ramfuncs : LOAD = FLASHD,
RUN = RAML0,
LOAD_START(_RamfuncsLoadStart),
//LOAD_END(_RamfuncsLoadEnd),
LOAD_SIZE(_RamfuncsLoadSize),
RUN_START(_RamfuncsRunStart),
PAGE = 0
csmpasswds : > CSM_PWL_P0 PAGE = 0
csm_rsvd : > CSM_RSVD PAGE = 0
/* Allocate uninitalized data sections: */
.stack : > RAMM0 PAGE = 1
.ebss : > RAML2 PAGE = 1
.esysmem : > RAML2 PAGE = 1
/* Initalized sections go in Flash */
/* For SDFlash to program these, they must be allocated to page 0 */
.econst : > FLASHA PAGE = 0
.switch : > FLASHA PAGE = 0
/* Allocate IQ math areas: */
IQmath : > FLASHA PAGE = 0 /* Math Code */
IQmathTables : > IQTABLES, PAGE = 0, TYPE = NOLOAD
/* Uncomment the section below if calling the IQNexp() or IQexp()
functions from the IQMath.lib library in order to utilize the
relevant IQ Math table in Boot ROM (This saves space and Boot ROM
is 1 wait-state). If this section is not uncommented, IQmathTables2
will be loaded into other memory (SARAM, Flash, etc.) and will take
up space, but 0 wait-state is possible.
*/
/*
IQmathTables2 : > IQTABLES2, PAGE = 0, TYPE = NOLOAD
{
IQmath.lib<IQNexpTable.obj> (IQmathTablesRam)
}
*/
/* Uncomment the section below if calling the IQNasin() or IQasin()
functions from the IQMath.lib library in order to utilize the
relevant IQ Math table in Boot ROM (This saves space and Boot ROM
is 1 wait-state). If this section is not uncommented, IQmathTables2
will be loaded into other memory (SARAM, Flash, etc.) and will take
up space, but 0 wait-state is possible.
*/
/*
IQmathTables3 : > IQTABLES3, PAGE = 0, TYPE = NOLOAD
{
IQmath.lib<IQNasinTable.obj> (IQmathTablesRam)
}
*/
/* .reset is a standard section used by the compiler. It contains the */
/* the address of the start of _c_int00 for C Code. /*
/* When using the boot ROM this section and the CPU vector */
/* table is not needed. Thus the default type is set here to */
/* DSECT */
.reset : > RESET, PAGE = 0, TYPE = DSECT
vectors : > VECTORS PAGE = 0, TYPE = DSECT
}
/*
//===========================================================================
// End of file.
//===========================================================================
*/
/*
//###########################################################################
//
// FILE: DSP2803x_Headers_nonBIOS.cmd
//
// TITLE: DSP2803x Peripheral registers linker command file
//
// DESCRIPTION:
//
// This file is for use in Non-BIOS applications.
//
// Linker command file to place the peripheral structures
// used within the DSP2803x headerfiles into the correct memory
// mapped locations.
//
// This version of the file includes the PieVectorTable structure.
// For BIOS applications, please use the DSP2803x_Headers_BIOS.cmd file
// which does not include the PieVectorTable structure.
//
//###########################################################################
// $TI Release: F2803x C/C++ Header Files and Peripheral Examples V127 $
// $Release Date: March 30, 2013 $
//###########################################################################
*/
MEMORY
{
PAGE 0: /* Program Memory */
PAGE 1: /* Data Memory */
DEV_EMU : origin = 0x000880, length = 0x000105 /* device emulation registers */
SYS_PWR_CTL : origin = 0x000985, length = 0x000003 /* System power control registers */
FLASH_REGS : origin = 0x000A80, length = 0x000060 /* FLASH registers */
CSM : origin = 0x000AE0, length = 0x000010 /* code security module registers */
ADC_RESULT : origin = 0x000B00, length = 0x000020 /* ADC Results register mirror */
CPU_TIMER0 : origin = 0x000C00, length = 0x000008 /* CPU Timer0 registers */
CPU_TIMER1 : origin = 0x000C08, length = 0x000008 /* CPU Timer0 registers (CPU Timer1 & Timer2 reserved TI use)*/
CPU_TIMER2 : origin = 0x000C10, length = 0x000008 /* CPU Timer0 registers (CPU Timer1 & Timer2 reserved TI use)*/
PIE_CTRL : origin = 0x000CE0, length = 0x000020 /* PIE control registers */
PIE_VECT : origin = 0x000D00, length = 0x000100 /* PIE Vector Table */
CLA1 : origin = 0x001400, length = 0x000080 /* CLA registers */
ECANA : origin = 0x006000, length = 0x000040 /* eCAN-A control and status registers */
ECANA_LAM : origin = 0x006040, length = 0x000040 /* eCAN-A local acceptance masks */
ECANA_MOTS : origin = 0x006080, length = 0x000040 /* eCAN-A message object time stamps */
ECANA_MOTO : origin = 0x0060C0, length = 0x000040 /* eCAN-A object time-out registers */
ECANA_MBOX : origin = 0x006100, length = 0x000100 /* eCAN-A mailboxes */
COMP1 : origin = 0x006400, length = 0x000020 /* Comparator + DAC 1 registers */
COMP2 : origin = 0x006420, length = 0x000020 /* Comparator + DAC 2 registers */
COMP3 : origin = 0x006440, length = 0x000020 /* Comparator + DAC 3 registers */
EPWM1 : origin = 0x006800, length = 0x000040 /* Enhanced PWM 1 registers */
EPWM2 : origin = 0x006840, length = 0x000040 /* Enhanced PWM 2 registers */
EPWM3 : origin = 0x006880, length = 0x000040 /* Enhanced PWM 3 registers */
EPWM4 : origin = 0x0068C0, length = 0x000040 /* Enhanced PWM 4 registers */
EPWM5 : origin = 0x006900, length = 0x000040 /* Enhanced PWM 5 registers */
EPWM6 : origin = 0x006940, length = 0x000040 /* Enhanced PWM 6 registers */
EPWM7 : origin = 0x006980, length = 0x000040 /* Enhanced PWM 7 registers */
ECAP1 : origin = 0x006A00, length = 0x000020 /* Enhanced Capture 1 registers */
HRCAP1 : origin = 0x006AC0, length = 0x000020 /* High Resolution Capture 1 registers */
HRCAP2 : origin = 0x006AE0, length = 0x000020 /* High Resolution Capture 2 registers */
EQEP1 : origin = 0x006B00, length = 0x000040 /* Enhanced QEP 1 registers */
LINA : origin = 0x006C00, length = 0x000080 /* LIN-A registers */
GPIOCTRL : origin = 0x006F80, length = 0x000040 /* GPIO control registers */
GPIODAT : origin = 0x006FC0, length = 0x000020 /* GPIO data registers */
GPIOINT : origin = 0x006FE0, length = 0x000020 /* GPIO interrupt/LPM registers */
SYSTEM : origin = 0x007010, length = 0x000020 /* System control registers */
SPIA : origin = 0x007040, length = 0x000010 /* SPI-A registers */
SPIB : origin = 0x007740, length = 0x000010 /* SPI-B registers */
SCIA : origin = 0x007050, length = 0x000010 /* SCI-A registers */
NMIINTRUPT : origin = 0x007060, length = 0x000010 /* NMI Watchdog Interrupt Registers */
XINTRUPT : origin = 0x007070, length = 0x000010 /* external interrupt registers */
ADC : origin = 0x007100, length = 0x000080 /* ADC registers */
I2CA : origin = 0x007900, length = 0x000040 /* I2C-A registers */
PARTID : origin = 0x3D7E80, length = 0x000001 /* Part ID register location */
CSM_PWL : origin = 0x3F7FF8, length = 0x000008 /* Part of FLASHA. CSM password locations. */
}
SECTIONS
{
/*** PIE Vect Table and Boot ROM Variables Structures ***/
UNION run = PIE_VECT, PAGE = 1
{
PieVectTableFile
GROUP
{
EmuKeyVar
EmuBModeVar
FlashCallbackVar
FlashScalingVar
}
}
/*** Peripheral Frame 0 Register Structures ***/
DevEmuRegsFile : > DEV_EMU, PAGE = 1
SysPwrCtrlRegsFile: > SYS_PWR_CTL, PAGE = 1
FlashRegsFile : > FLASH_REGS, PAGE = 1
CsmRegsFile : > CSM, PAGE = 1
AdcResultFile : > ADC_RESULT, PAGE = 1
CpuTimer0RegsFile : > CPU_TIMER0, PAGE = 1
CpuTimer1RegsFile : > CPU_TIMER1, PAGE = 1
CpuTimer2RegsFile : > CPU_TIMER2, PAGE = 1
PieCtrlRegsFile : > PIE_CTRL, PAGE = 1
Cla1RegsFile : > CLA1, PAGE = 1
/*** Peripheral Frame 1 Register Structures ***/
ECanaRegsFile : > ECANA, PAGE = 1
ECanaLAMRegsFile : > ECANA_LAM, PAGE = 1
ECanaMboxesFile : > ECANA_MBOX, PAGE = 1
ECanaMOTSRegsFile : > ECANA_MOTS, PAGE = 1
ECanaMOTORegsFile : > ECANA_MOTO, PAGE = 1
ECap1RegsFile : > ECAP1, PAGE = 1
HRCap1RegsFile : > HRCAP1, PAGE = 1
HRCap2RegsFile : > HRCAP2, PAGE = 1
EQep1RegsFile : > EQEP1, PAGE = 1
LinaRegsFile : > LINA, PAGE = 1
GpioCtrlRegsFile : > GPIOCTRL, PAGE = 1
GpioDataRegsFile : > GPIODAT, PAGE = 1
GpioIntRegsFile : > GPIOINT, PAGE = 1
/*** Peripheral Frame 2 Register Structures ***/
SysCtrlRegsFile : > SYSTEM, PAGE = 1
SpiaRegsFile : > SPIA, PAGE = 1
SpibRegsFile : > SPIB, PAGE = 1
SciaRegsFile : > SCIA, PAGE = 1
NmiIntruptRegsFile: > NMIINTRUPT, PAGE = 1
XIntruptRegsFile : > XINTRUPT, PAGE = 1
AdcRegsFile : > ADC, PAGE = 1
I2caRegsFile : > I2CA, PAGE = 1
/*** Peripheral Frame 3 Register Structures ***/
Comp1RegsFile : > COMP1, PAGE = 1
Comp2RegsFile : > COMP2, PAGE = 1
Comp3RegsFile : > COMP3, PAGE = 1
EPwm1RegsFile : > EPWM1, PAGE = 1
EPwm2RegsFile : > EPWM2, PAGE = 1
EPwm3RegsFile : > EPWM3, PAGE = 1
EPwm4RegsFile : > EPWM4, PAGE = 1
EPwm5RegsFile : > EPWM5, PAGE = 1
EPwm6RegsFile : > EPWM6, PAGE = 1
EPwm7RegsFile : > EPWM7, PAGE = 1
/*** Code Security Module Register Structures ***/
CsmPwlFile : > CSM_PWL, PAGE = 1
/*** Device Part ID Register Structures ***/
PartIdRegsFile : > PARTID, PAGE = 1
}
/*
//===========================================================================
// End of file.
//===========================================================================
*/
