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28335 data address bus width

tathvamasi
Prodigy 250 points

Hi,

I would like to know why the data address bus width in the 28335 is of 32 bit width. Since memory is mapped uniformly in both program and data space, I would assume that a 22 bit data address width similar to that for the program address bus, would be sufficient. Then why is this designed so?


Thanks in advance.

  • 0
    TI__Prodigy 240 points

    The maximum size of an instruction in the C28 CPU is 32 bits.  This includes the decode fo the instruction operation and any immediate data necessary to complete the instruction.  At least 10 bits are necessary to decode the specific operation (Branch/Call) leaving 32-10=22 bits left over as the maximum address range of program space.  The data address generation can be loaded via memory locations, over a 32-bit bus, and therefore can support up to 32 bits. 

    For example binary image of a long branch (LB LONGADDRESS32BITSWIDEE) instruction is 0000 0000 01LO NGAD DRES S32B ITSW IDEE.  You see there are only 22 bits available to define the long address.

    The binary image of a load of MOVL XAR5,LOCATION instruction is 1100 0011 LOCA TION.  The 8 bits (LOCATION) defines a 32 bit address from which a 32 bit value may be loaded into the 32 bit register XAR5.  This register is a pointer to anywhere in data space so data space is bigger than program space. 

    So the limitation in program space has to do with instruciton decode and does not apply to the address range of data space. 

    Does this answer your question?