Interfacing Concerto F28M35x with Spartan-6 Xilinx

Please note that on this device we have EPI module insted of XINTF, which can be used for this.

Regards,

Vivek Singh

Thank you for your answers.

The problem is that we are not sure what is the analog part to EPI on the Spartan-6. Is there also sample code to setup the FPGA to communicate via EPI?

user4452252 said:

Is there also sample code to setup the FPGA to communicate via EPI?

No there's no sample code for the above interface. But you can refer epi-sdram interface:

C:\ti\controlSUITE\device_support\f28m35x\v206\F28M35x_examples_Master\epi_sdram

Regards,

Gautam

Hello,

I have the Concerto F28M35x Evalboard and I am just wondering how can I get access to the following GPIO pins for EPI Bus:

I only found a few, marked with a *:

 -     *EPI0S0(D0)        -    PH3_GPIO51        EPI0S1(D1)    -    PH2_GPIO50
//! -     EPI0S2(D2)        -    PC4_GPIO68        EPI0S3(D3)    -    PC5_GPIO69
//! -     EPI0S4(D4)        -    PC6_GPIO70        EPI0S5(D5)    -    PC7_GPIO71
//! -     EPI0S6(D6)        -    PH0_GPIO48        EPI0S7(D7)    -    PH1_GPIO49
//! -     EPI0S8(A0)        -    PE0_GPIO24        EPI0S9(A1)    -    PE1_GPIO25
//! -     EPI0S10(A2)       -    PH4_GPIO52        EPI0S11(A3)   -    PH5_GPIO53
//! -     EPI0S12(A4)      -    PF4_GPIO36        EPI0S13(A5)   -    PG0_GPIO40
//! -     EPI0S14(A6)       -    PG1_GPIO41        EPI0S15(A7)   -    PF5_GPIO37
//! -     EPI0S16(A8)       -    PJ0_GPIO56        EPI0S17(A9)   -    PJ1_GPIO57
//! -     EPI0S18(A10)      -    PJ2_GPIO58        EPI0S19(A11)  -    PJ3_GPIO59
//! -     EPI0S20(A12)      -    PD2_GPIO18        EPI0S21(A13)  -    PD3_GPIO19
//! -     EPI0S22(A14)      -    PB5_GPIO13        EPI0S23(A15)  -    PB4_GPIO12
//! -     EPI0S24(A16)      -    PE2_GPIO26        EPI0S25(A17)  -    PE3_GPIO27
//! -     EPI0S26(A18)      -    PH6_GPIO54        EPI0S27(iRDY) -    PH7_GPIO55
//! -     *EPI0S28(WR)       -    PJ4_GPIO60        EPI0S29(RD)   -    PJ5_GPIO61
//! -     *EPI0S30(Frame)  -    PJ6_GPIO62        EPI0S31(CLK)  -    PG7_GPIO47

//! \b EPI \b peripheral
//!
//! - EPI0S0(D0) - PH3_GPIO51(*) EPI0S1(D1) - PH2_GPIO50(-)
//! - EPI0S2(D2) - PC4_GPIO68(-?) EPI0S3(D3) - PC5_GPIO69(*)
//! - EPI0S4(D4) - PC6_GPIO70(-) EPI0S5(D5) - PC7_GPIO71 (-)
//! - EPI0S6(D6) - PH0_GPIO48(**TP18)EPI0S7(D7) - PH1_GPIO49(*)
//! - EPI0S8(A0) - PE0_GPIO24 * EPI0S9(A1) - PE1_GPIO25 *
//! - EPI0S10(A2) - PH4_GPIO52(*) EPI0S11(A3) - PH5_GPIO53(*)
//! - EPI0S12(A4) - PF4_GPIO36(-) EPI0S13(A5) - PG0_GPIO40(*)
//! - EPI0S14(A6) - PG1_GPIO41(*) EPI0S15(A7) - PF5_GPIO37(*)
//! - EPI0S16(A8) - PJ0_GPIO56(*) EPI0S17(A9) - PJ1_GPIO57(*)
//! - EPI0S18(A10) - PJ2_GPIO58* EPI0S19(A11) - PJ3_GPIO59*
//! - EPI0S20(A12) - PD2_GPIO18* EPI0S21(A13) - PD3_GPIO19*
//! - EPI0S22(A14) - PB5_GPIO13* EPI0S23(A15) - PB4_GPIO12*
//! - EPI0S24(A16) - PE2_GPIO26* EPI0S25(A17) - PE3_GPIO27*
//! - EPI0S26(A18) - PH6_GPIO54(*) EPI0S27(iRDY) - PH7_GPIO55(*)
//! - EPI0S28(WR) - PJ4_GPIO60* EPI0S29(RD) - PJ5_GPIO61*
//! - *EPI0S30(Frame) - PJ6_GPIO62 EPI0S31(CLK) - PG7_GPIO47(*)

Could you point me to the document you are referring for this.

Regards,

Vivek Singh

Hello Vivek,

I am refering to this document, page 6:

ftp.ti.com/.../F28M35xx_InfoSheet_Rev1%200_09_07_11%20Release.pdf

But I have the updated Version from 06/08/11 on my CD. I have found all the GPIO Ports marked with a * or (*), but some are missing marked with a - in my previous post.
 I would like to implement the EPI bus with 8 wire databus and 4 wire adressbus. Which GPIO Ports could you recomend?

Hi,

Are you coding your own program for Spartan-6 Xilinx or it has it's own interface which you want to interface with EPI?

Also please go through the description of GPIO mode of EPI in TRM (section "19.8 General-Purpose Mode") and let us know if you have some specific question about it.

Regards,

Vivek Singh

Hello,

I have no specific Interface on the Xillinx side, so I will write my own. And the FPGA will be the EPI slave.

I am refering to table19-9.EPI General-Purpose Signal Connections, page 1381http://www.ti.com/lit/ug/spruh22g/spruh22g.pdf

There are four modes mentioned:

--- D8, A20

--- D16, A12

--- D24, A4

--- D32

The problem is that the EPI Signals are linked to the GPIO Ports and I can´t find all the necessary GPIO Pins on my Hardware evaluation board.

Table 4.1 GPIO Pins and Alternate Function, page 338 http://www.ti.com/lit/ug/spruh22g/spruh22g.pdf

I would like to use the first mode D8, A20, page 1381

(D0):  EPI0S0   ->    PH3_GPIO51, GPIO Pin 51 is on my evaluation board

(D1): EPI0S1    ->   PH2_GPIO50, GPIO Pin 50 is NOT on the evaluation board

(D2): EPI0S2    ->    PC4_GPIO68, GPIO Pin 68 is NOT on the evaluation board

(D3): EPI0S3)   ->    PC5_GPIO69, GPIO Pin 69 is on my evaluation board

(D4): EPI0S4    ->    PC6_GPIO70,  GPIO Pin 70 is NOT on the evaluation board 

(D5): EPI0S5    ->    PC7_GPIO71, GPIO Pin 71 is NOT on the evaluation board 

(D6): EPI0S6    ->    PH0_GPIO48, GPIO Pin 48 is NOT on the evaluation board, TEST PIN 18

(D7): EPI0S7    ->    PH1_GPIO49, GPIO Pin 49 is on my evaluation board

MY QUESTION: How can I use the EPI Inteface if I can´t finde the necessary GPIO Pins on the Hardware.

ftp.ti.com/.../F28M35xx_InfoSheet_Rev1%200_09_07_11%20Release.pdf

Is there any opportunity to use other EPI Signals for my Data and therefore other GPIO Pins.

ftp.ti.com/pub/dml/DMLrequest/Christy_FTP-10-30-12/controlSUITE/development_kits/~ExperimentersKits/F28M35xx_InfoSheet_Rev1 0_09_07_11 Release.pdf