• State
  • Locked Locked
  • Replies 4 replies
  • Subscribers 83 subscribers
  • Views 1785 views
  • Users 0 members are here
Support feedback
Options
Options
Related

This thread has been locked.

If you have a related question, please click the "Ask a related question" button in the top right corner. The newly created question will be automatically linked to this question.

Comparator Block F28069 - Ramp Generator - Peak Current Mode Control

Stefan Klammer
Prodigy 40 points


Hi all,

i'm trying to make a synchronous Buck Converter with Peak Current Mode Control. To do that i have configured EPWM1 to make a 150 kHz Gatesignals. With COMP2 i made a Peak Current detection with Compensation Ramp. During testing i figured out that if the comparator and the current measurement crossing each other shortly before the pwm cycle is over, i get a pwm cycle with maximum duty cycle and after that one with a extremely low dutycycle like in the picture.

In the attached file there is a project which i have used to reproduce this effect on a Control Card with Dockingstation.

The Gatesignals are on GPIO0 & 1
The comparator is on A4

To see the effect you have to connect a Voltage of about 1.63V on Pin A4.
If the voltage goes lower the Comparator the epwm will be shut down at a dutycyle of 93%. If the Voltage goes higher the comparator works as expected.

Would be great if someone has a tip for me or can reproduce this effect.

Thanks for your help,

Best regards

StefanDigitalCompareRamptest.zip

  • 0
    TI__Mastermind 27200 points

    Stefan,

    The most likely explanation is there is ringing at the input to the comparator after the PWM trips.  When the trip point gets near to the counter period the transient doesn't have time to completely decay - some of it spills over into next PWM cycle and it's enough to trip the PWM.  You may be able to verify this by looking at the comparator input pin with a 'scope.

    One thing you could try if you know the comparator trip will happen near the PWM period, is to invert blanking polarity and use the DCFOFFSET register to enable the trip just before the period match.  

    You might also try to filter the glitches at the comparator output by entering something in the QUALSEL field of the COMPCLT register, but be aware this will increase latency at the comparator output.

    Regards,

    Richard

  • 0 in reply to Richard Poley
    Prodigy 40 points
    Hello Richard,

    thank you for your fast reply. I verified the effect also on the evaluation board without the power electronics part so the ringing you mentioned is not the problem i think. I tried again with the blanking window and i got it working with that. Now i blank the comparator for 100 cycles starting at 550 so the whole switch off section is blanked.

    At the moments it looks good that i will work,
    Thanks again for the fast helpful reply,

    Best Regards ,
    Stefan
  • 0 in reply to Stefan Klammer
    TI__Mastermind 27200 points

    Stefan,

    Glad to know you got it working.  Thanks for posting back to let us know.

    The effect is interesting.  If it's not a glitch, the only thing I can think of is the DCFWINDOW register setting.  It should be in the range 0 to 0xFF (you have 0x2FF, so one bit in the reserved field is being set).  

    It probably doesn't matter if you have it working, but if you need to go back to your original code for some reason it would be worth trying 0xFF in case it makes a difference.  

    Thanks again.

    Best regards,

    Richard

  • 0 in reply to Richard Poley
    TI__Genius 10820 points

    Hi Stefan,

    I am glad this is working for you. Using the blanking window, QUALSEL and DCFWINDOW adjustment is the right approach. I don't think you need this anymore but if you want you may use the DPS workshop software as reference (http://processors.wiki.ti.com/index.php/C2000_DPSWorkshop).

    Hrishi