F2806x McBSP as SPI master Issues.

Other Parts Discussed in Thread: CONTROLSUITE

Hello

I am using the McBSP in SPI master mode on my F28067, in my SPI communication I have to control one sensor.

The message sent perfectly, CLKX, DX DR and FSX are good. (verify to oscilloscope)

but I don't understand, I've sent Dx normaly and the sensor operates, yet in the DR register I can't write good data, in  Dr I receive the Dx register.

Could you help me ?

Thanks in advance.

void init_dma()
{
  EALLOW;
  DmaRegs.DMACTRL.bit.HARDRESET = 1;
 __asm(" NOP");						   			// Only 1 NOP needed per Design
  DmaRegs.CH1.MODE.bit.CHINTE = 0;
  // Channel 1, McBSPA transmit
  DmaRegs.CH1.BURST_SIZE.all = 0;				// 1 word/burst
  DmaRegs.CH1.SRC_BURST_STEP = 0;				// no effect when using 1 word/burst
  DmaRegs.CH1.DST_BURST_STEP = 0;				// no effect when using 1 word/burst
  DmaRegs.CH1.TRANSFER_SIZE = 127;				// Interrupt every frame (127 bursts/transfer)
  DmaRegs.CH1.SRC_TRANSFER_STEP = 1;			// Move to next word in buffer after each word in a burst
  DmaRegs.CH1.DST_TRANSFER_STEP = 0;			// Don't move destination address
  DmaRegs.CH1.SRC_ADDR_SHADOW = (Uint32) &Sdata[0];					// Start address = buffer
  DmaRegs.CH1.SRC_BEG_ADDR_SHADOW = (Uint32) &Sdata[0];				// Not needed unless using wrap function
  DmaRegs.CH1.DST_ADDR_SHADOW = (Uint32) &McbspaRegs.DXR1.all;		// Start address = McBSPA DXR
  DmaRegs.CH1.DST_BEG_ADDR_SHADOW = (Uint32) &McbspaRegs.DXR1.all;	// Not needed unless using wrap function
  DmaRegs.CH1.CONTROL.bit.PERINTCLR = 1;		// Clear peripheral interrupt event flag

  DmaRegs.CH1.CONTROL.bit.ERRCLR = 1;			// Clear sync error flag
  DmaRegs.CH1.DST_WRAP_SIZE = 0xFFFF;			// Put to maximum - don't want destination wrap
  DmaRegs.CH1.SRC_WRAP_SIZE = 0xFFFF;			// Put to maximum - don't want source wrap


  DmaRegs.CH1.MODE.bit.CHINTE = 1;				// Enable channel interrupt
  DmaRegs.CH1.MODE.bit.CHINTMODE = 1;			// Interrupt at end of transfer
  DmaRegs.CH1.MODE.bit.PERINTE = 1;				// Enable peripheral interrupt event
  DmaRegs.CH1.MODE.bit.PERINTSEL = DMA_MXEVTA;		// Peripheral interrupt select = McBSP 0A
  DmaRegs.CH1.CONTROL.bit.PERINTCLR = 1;  			// Clear any spurious interrupt flags

  // Channel 2, McBSPA Receive
  DmaRegs.CH2.MODE.bit.CHINTE = 0;
  DmaRegs.CH2.BURST_SIZE.all = 0;				// 1 word/burst
  DmaRegs.CH2.SRC_BURST_STEP = 0;				// no effect when using 1 word/burst
  DmaRegs.CH2.DST_BURST_STEP = 0;				// no effect when using 1 word/burst
  DmaRegs.CH2.TRANSFER_SIZE = 127;				// Interrupt every 127 bursts/transfer
  DmaRegs.CH2.SRC_TRANSFER_STEP = 0;			// Don't move source address
  DmaRegs.CH2.DST_TRANSFER_STEP = 1;			// Move to next word in buffer after each word in a burst
  DmaRegs.CH2.SRC_ADDR_SHADOW = (Uint32) &McbspaRegs.DRR1.all;			// Start address = McBSPA DRR
  DmaRegs.CH2.SRC_BEG_ADDR_SHADOW = (Uint32) &McbspaRegs.DRR1.all;		// Not needed unless using wrap function
  DmaRegs.CH2.DST_ADDR_SHADOW = (Uint32) &Rdata[0];		// Start address = Receive buffer (for McBSP-A)
  DmaRegs.CH2.DST_BEG_ADDR_SHADOW = (Uint32) &Rdata[0];	// Not needed unless using wrap function
  DmaRegs.CH2.CONTROL.bit.PERINTCLR = 1;		// Clear peripheral interrupt event flag

  DmaRegs.CH2.CONTROL.bit.ERRCLR = 1;			// Clear sync error flag
  DmaRegs.CH2.DST_WRAP_SIZE = 0xFFFF;			// Put to maximum - don't want destination wrap
  DmaRegs.CH2.SRC_WRAP_SIZE = 0xFFFF;			// Put to maximum - don't want source wrap
  DmaRegs.CH2.MODE.bit.CHINTE = 1;				// Enable channel interrupt
  DmaRegs.CH2.MODE.bit.CHINTMODE = 1;			// Interrupt at end of transfer
  DmaRegs.CH2.MODE.bit.PERINTE = 1;				// Enable peripheral interrupt event
  DmaRegs.CH2.MODE.bit.PERINTSEL = DMA_MREVTA;  // Peripheral interrupt select = McBSP MRSYNCA
  DmaRegs.CH2.CONTROL.bit.PERINTCLR = 1;  		// Clear any spurious interrupt flags
  EDIS;
}