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F28377S EPWM Frequency halves ?

Salman Ahmed97
Prodigy 110 points


Hi there

I am using F28377S Launchpad and am trying to set a 50us Time period for my EPWM.

Now I know the the EPWMCLK is half of SYSCLK if SYSCLK = 200 Mhz. So keeping that into account, I calculated the TBPRD value using figure 12-6 from the manual but still the frequency of the EPWM is half.

My settings are as follows:

// Setup TBCLK
EPwm2Regs.TBCTL.bit.CTRMODE = TB_COUNT_UP; // Count up
EPwm2Regs.TBPRD = EPWM2_TIMER_TBPRD; // Set timer period (timer value is 4999) 
EPwm2Regs.TBCTL.bit.PHSEN = TB_DISABLE; // Disable phase loading
EPwm2Regs.TBPHS.bit.TBPHS = 0x0000; // Phase is 0
EPwm2Regs.TBCTR = 0x0000; // Clear counter
EPwm2Regs.TBCTL.bit.HSPCLKDIV = 0x0; // Clock ratio to SYSCLKOUT
EPwm2Regs.TBCTL.bit.CLKDIV = 0x0;

// Setup shadow register load on ZERO
EPwm2Regs.CMPCTL.bit.SHDWAMODE = CC_SHADOW;
EPwm2Regs.CMPCTL.bit.SHDWBMODE = CC_SHADOW;
EPwm2Regs.CMPCTL.bit.LOADAMODE = CC_CTR_ZERO;
EPwm2Regs.CMPCTL.bit.LOADBMODE = CC_CTR_ZERO;

// Set Compare values
EPwm2Regs.CMPA.bit.CMPA = EPWM2_TIMER_TBPRD/2; // Set compare A value
EPwm2Regs.CMPB.bit.CMPB = EPWM2_TIMER_TBPRD/2; // Set Compare B value

// Set actions
EPwm2Regs.AQCTLA.bit.PRD = AQ_CLEAR; // Clear PWM2A on Period
EPwm2Regs.AQCTLA.bit.CAU = AQ_SET; // Set PWM2A on event A, up count

EPwm2Regs.AQCTLB.bit.PRD = AQ_CLEAR; // Clear PWM2B on Period
EPwm2Regs.AQCTLB.bit.CBU = AQ_SET; // Set PWM2B on event B, up count

// Interrupt where we will change the Compare Values
EPwm2Regs.ETSEL.bit.INTSEL = ET_CTR_ZERO; // Select INT on Zero event
EPwm2Regs.ETSEL.bit.INTEN = 1; // Enable INT
EPwm2Regs.ETPS.bit.INTPRD = 0x01; // Generate INT on 1 event

Using the above settins, the value of timer calculated is

TBCLK = 100e6/(1*1) = 100e6 ;

Time period of TBCLK = 10nsec 

TBPRD = (50e-6/10e-9 ) -1 = 4999

I check the frequency on oscilloscope and I get 100usec time period.

I wonder what I am missing ? 

Regards

Salman

  • 0
    TI__Mastermind 27200 points

    Salman,

    There's nothing apparently wrong with the code in your post.  Can you re-check the clocking registers to be sure they are configured as you think?

    Start with the SYSPLLMULT register, and the PLLSYSCLKDIV field in the SYSCLKDIVSEL register.  Check that your clock source frequency, together with those register settings, give you 200MHz SYSCLK.  The PERCLKDIVSEL field in EPWMCLKDIV should divide that by 2.

    Regards,

    Richard

  • 0 in reply to Richard Poley
    TI__Mastermind 24095 points

    Hi Salman,

    This could be due to the 10MHz crystal on the launch pad? What is your clock source? Is it on chip internal oscillator or crystal?
    Please adjust PLL multiplier according to the source clock.

    -Bharathi.

  • 0 in reply to Subrahmanya
    Prodigy 110 points

    It turns out I messed up in the PLL. Was  multiplying by 20 rather than 40.

    Corrected

    PLLSYSCLK = 10Mhz(OSCCLK) * 40 (IMULT) * 1 (FMULT) /  2 (PLLCLK_BY_2) = 200 Mhz .