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F2837xD booting both CPUs from Flash

jimj2713
Expert 2395 points

I have a dual-CPU project, with both CPUs booting from Flash, and copying much of the ISR-code into RAM for the fastest operation. Both of these CPUs run seemingly reliably within the debugger. However when I power-cycle, CPU2 either doesn't boot or runs to an ESTOP or some significant failure like that.

I have inter-processor communication working (within the debugger), and my boot-sequence is as follows:

The first thing CPU2 does is spin on IPC17:

   while (IpcRegs.IPCSTS.bit.IPC17 == 0);  // Wait for CPU01 to set IPC17
   IpcRegs.IPCACK.bit.IPC17 = 1;          // Acknowledge and clear IPC17

Within CPU1, I initialize almost every peripheral (including the shared-RAM segregation between CPUs), and at the end of init, I set IPC17. Then CPU2 can initialize its peripherals and copy its ISR code from Flash to RAM.

I have limited debug capability, because this only fails after a power-cycle. I know from the RSTSTAT register that CPU2 is not held in reset, but it also does not appear to be executing. Any ideas or suggestions I might look at?

Thanks,

Jim

  • 0
    TI__Guru** 116811 points

    Hi Jim,

    Look like in your setup proper BOOT option is not used for CPU2,  hence it's in "Wait BOOT" when in stand alone mode.

    Please go through section "3.11 Boot Modes Supported on CPU2" of TRM  which explains the boot process for CPU2.

    Also following forum post have more detail on how to boot CPU2 from CPU1.

    https://e2e.ti.com/support/microcontrollers/c2000/f/171/t/395895

    Regards,

    Vivek Singh

  • 0 in reply to Vivek Singh
    Expert 2395 points
    It looks like I have to program the OTP to instruct the CPU2 to boot from Flash. the zone-selection was unclear -- does it matter which zone (1 or 2) I choose to program for CPU2?
    Thanks,
    Jim
  • 0 in reply to jimj2713
    TI__Guru** 116811 points

    Hi Jim,

    You can program BOOTCTRL location of either of Zone.  This is shown in "Figure 3-1. BOOTCTRL Selection (applies to both the CPUs)" of TRM.

    Also you don't need to program this register to BOOT CPU2. This can be done using IPC command also. Please refer section "3.18 Boot and IPC Commands" of TRM for the same.

    Regards,

    Vivek Singh

  • 0 in reply to Vivek Singh
    Expert 2395 points
    That 3.18 section is a bit difficult to decipher, but it looks like I should be able to add only this line in CPU1:
    IpcRegs.IPCBOOTMODE = C1C2_BROM_BOOTMODE_BOOT_FROM_FLASH;

    However, my CPU2 still does not boot (outside of the debugger). IPCBOOTMODE is not EALLOW protected, and I updated IPCBOOTMODE after configuring the GPIO. Also the GPIO72/84 are configured to boot from Flash.

    Any thing else you can think of?
    Thanks,
    Jim
  • 0 in reply to jimj2713
    Expert 2395 points
    Just some updated information. I believe the CPU1-to-CPU2 boot-from-flash command is:
    IpcRegs.IPCRECVCOM = 19;
    IpcRegs.IPCBOOTMODE = C1C2_BROM_BOOTMODE_BOOT_FROM_FLASH; //0x0B
    IpcRegs.IPCSENDCOM = BROM_IPC_EXECUTE_BOOTMODE_CMD; //Not sure if this is necessary.

    Which still doesn't work. I tried using the IPCBootCPU2() code from the Ipc_driver.c, but it hangs on the section:
    do
    {
    bootStatus = IPCGetBootStatus() & 0x0000000F;
    } while ((bootStatus != C2_BOOTROM_BOOTSTS_SYSTEM_READY));

    But I don't think this code would accomplish what I am attempting because the C2_BOOTROM_BOOTSTS_SYSTEM_READY status indicates "CPU2 has completed the boot and is ready for C1TOC2 IPC commands" -- and I want to communicate with the CPU2 boot-rom.

    I also tried reading the IPCBOOTSTS and IPCREMOTEREPLY (NAK-status), but the data does not match the table in section 3.17. The NAK-status is 0, which I think means my commands above were not NAKed. However the CPU2 boot-status was 0xD02, which does not map to a specified return value in table 3.17.3.

    Is it possible the CPU2 boot-rom is not running here? Is there another register I can read to determine the CPU2 status?

    Thanks,
    Jim
  • 0 in reply to jimj2713
    TI__Guru** 116811 points

    Hi Jim,

    Please have a look at the steps mentioned in below post.

    https://e2e.ti.com/support/microcontrollers/c2000/f/171/t/424621

    Also please note that that BOOT-STATUS in one-hot encoded. So every individual bit has a meaning not the full world.

    Regards,

    Vivek Singh

  • 0 in reply to Vivek Singh
    Expert 2395 points
    Vivek,
    Michael's example code in the link above helped me fix the problem. I was already close, but I was fooled by the fact the line:
    do ... while ((bootStatus != C2_BOOTROM_BOOTSTS_SYSTEM_READY));
    will hang in emulation mode -- because the CPU2 boot-rom is not running.

    Besides an ifdef DEBUG (to exclude the do while code above), is there a nice way to determine is CPU2 is already running, so that this code would run both in emulation and normally?

    Thanks,
    Jim
  • 0 in reply to jimj2713
    TI__Guru** 116811 points

    Hi Jim,

    Good to know that your issue is resolved.

    We have a RESC register (see Figure 2-177. RESC Register) which has status bit "TRSTn_pin_status". This reflect the status of TRSTn pin which will be set to "1" in emulation else it'll be '0'. You could try this to determine the emaulation mode and normal mode.

    Regards,

    Vivek Singh

  • 0 in reply to Vivek Singh
    Intellectual 350 points
    My company can't have different builds for emulator/non-emulator modes, so we ended up adding this line at the very beginning of Core2 main code (right after InitSysCtrl()):

    IpcRegs.IPCBOOTSTS = C2_BOOTROM_BOOTSTS_SYSTEM_READY;

    That will prevent a stall in emulation mode, and in non-emulation mode the value of this register has already been set to C2_BOOTROM_BOOTSTS_C2TOC1_BOOT_CMD_ACK at this point and the register is no longer used.

    Vivek, do you see any problems in doing it like this?

    /Michael
  • 0 in reply to Michael Rindsig
    Expert 2395 points

    Thank you both. All is well now.

    Jim

  • 0 in reply to Michael Rindsig
    TI__Guru** 116811 points

    Michael,

    I think this should be fine too.

    Regards,

    Vivek Singh