WatchDog flag detection

Githin George

Other Parts Discussed in Thread: CONTROLSUITE, TMS320F28021

I am using F28021 controller, and I am trying to detect a watchdog reset. For that I am looking WDCR flag bit, But the controller is always showing a high value.

The value read from the controller is 0x00C0

How can I solve this issue?

over 10 years ago

0 Gautam Iyer over 10 years ago

Guru 192875 points

Hi,

Did you first check with the example file present here : C:\ti\controlSUITE\device_support\f2802x\v230\f2802x_examples_structs\watchdog

Regards,
Gautam

0 Vivek Singh over 10 years ago

TI__Guru** 115411 points

For more detail on WD, you can refer following wikipage also.

http://processors.wiki.ti.com/index.php/WDFlag_on_Piccolo

Regards,

Vivek Singh

0 Githin George over 10 years ago in reply to Gautam Iyer

Intellectual 290 points

Yes, When I debug with JTAG its showing correct value(0x0040), But when I stop debug and check the value I am getting always 0x00C0

0 Githin George over 9 years ago in reply to Vivek Singh

Intellectual 290 points

Hi Vivek,
From the wiki processors.wiki.ti.com/.../WDFlag_on_Piccolo , to distinguish between watchdog reset and power on reset, the XRS pin should be low minimum for about 3.7mSec. In my controller TMS320F28021, the XRS delay is about 1mSec. If I add a RC delay will it affect WATCHDOG reset pulse, means WATCHDOG will pull XRS low for about 60uSec and after that the RC delay will charge slowly and point XRS as low during the sample of WDFLAG(after 3.7mSec). This may cause to point a WATCHDOG reset as Power On reset.

0 Adam Haun over 9 years ago in reply to Githin George

TI__Expert 8950 points

Thw WDFLAG state is determined by the state of the XRS pin ~3.3 milliseconds after the reset. There are three conditions here:

1. Watchdog reset. The XRS pin must go high in less than 3.3 milliseconds. (It typically goes high after 512 OSCCLK cycles, which is 50-60 microsecond.) This will set WDFLAG.

2. External reset. The XRS pin must remain low for longer than 3.7 milliseconds to clear WDFLAG.

3. Power-on reset. The XRS pin must be held low for longer than 3.7 milliseconds to keep WDFLAG cleared. This can be done with a supervisor IC or an R-C circuit, as described in section 2B of the Wiki page.

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WatchDog flag detection