How to balance the motor control priority with ADC interrupt and SPI communication

I suggest leaving the ADC interrupt as higher priority, and manage the SPI interface outside of any ISR. The reason is because the control of the currents and execution of the estimator must be executed as soon as the ADC interrupt is present, otherwise, if the ADC interrupt needs to wait for other tasks to be completer (i.e. a SPI interrupt to be completed) you might miss the entire ADC interrupt, and overwrite the ADC result registers, causing a spike in the current (worst case causing an overcurrent, or a lost in field orientation)

We do have code right now in the DRV830x kits that read and write to the SPI port in the background loop. If the commanded speed is transmitted through the SPI port, I don't see the issue of putting this in the background loop. Is there any time critical message or command sent through the SPI port?

Alternatevely, I would suggest keeping the SPI without interrupts, and check if there is information in the receive buffer inside the ADC ISR. That way, you can re-utilize an existing interrupt that happens periodically.

Thanks,

-Jorge

Hi Jorge, 

1. If we want to manage SPI, SCI, I2C etc. all in the background loop, what scheduler algorithm you'll suggest to use ? 

will priority-based scheduler enough for the motor control communication implementation ?

Thanks,

Yz 

Disabling interrupts is a pretty strong measure. But as we do not know your application specifics (speed, data throughoutput, ...) it is the one the will work for certain.

My recomendations would be:

1. use FIFOs on all communication peripherals

2. you can use interrupts for communication but make sure you enable ADC interrupt within communication interupts to allow nesting and thus fast response of current control loop. This setup works fine for me, but you do need to handle shared data carefuly.

hi,

First of all, your control loop isr MUST have the highest priority. I mean that sampling time of control loop must be the same for all time. Otherwise, control algorithms (like integral or derivative operations) do NOT work correctly.

Secondly, I do motor control and also use SPI communication in the same project. But I dont have any problem. So it is theoretically + practically possible. What I do is, I call SPI communation in a (lower priority) timer ISR and my MCU is SPI master. If you use spi in slave mode, that could be a problem, because MCU cant do motor control and SPI communation at the same time. So if your SPI is in slave mode, try to change it to master mode if it is possible.

Lastly, do not do extra and unnecessary operations in motor control loop. Because it is called too often and because of that it consumes a lot of processing power. If you have extra operations, you should do them in lower priority isr. Moreover, I suggest you to measure CPU load of your control loop isr. In my practice, it should be less than 50%. If it is more, you do something wrong. You can measure it by toggling gpio and using oscilloscope.

Regards,
Hakan

Hi Mitja, 

1. Could you please be more specific about how to using FIFO and handle shared data? Do you mean use SPI buffer FIFO?

2. Also could you please explain more how you nested ADC interrupt within communication interrupts ? not the other way around nested communication ISR inside ADC ?

Thanks,

Yz

Hi Hakan,

Thanks a lot for all the detail explanation.
1) Will the control algorithm ISR still has to wait the SPI ISR completed even when I put the control algorithm ISR to the highest level ? I understand it will serve the control ISR first, but let's say there's a scenario that when the SPI is executing but the motor control ISR happens.
2) Just wondering how we priority timer ISR ?

Thanks,
Yz

Hi Yz,

Normally control operation in your control ISR should take some microseconds. So it is fast as lightning. Moreover, because control ISR has the highest priorty, it stops other ISRs, even they are executing. After control ISR is finished, other ISR can continue what they are doing. In my case, my control operations runs in EPWM isr, which runs at more than 10 Khz, but it takes only few microseconds to execute. I have also longer tasks like SCI and SPI communications. I do them in a timer isr. The trick is, when I enter the timer ISR, I re-enable global ISR and let PWM ISR to interrupt timer ISR. So my execution is like this. In this example 3x control ISR and 1x timer ISR is called.

Nope
Nope
Nope
Nope
Control ISR
Nope
Timer ISR ---- Here comes the timer isr with low priority jobs like communication.
Timer ISR
Timer ISR
Control ISR ---- control isr interrupts timer isr.
Timer ISR ---- timer isr continues.
Timer ISR
Timer ISR
Timer ISR
Control ISR ----- again control isr interrupts.
Timer ISR ----- timer continues.
Timer ISR
Timer ISR
Nope --- timer isr finished
...
...

So control isr blocks SPI as well, but because my DSP is SPI master, it decides on the SPI line when to communicate or not. So I don't lose any data because of control ISR interruption. But this will definitely not work in the case where DSP is SPI slave. In order not to lose any data during SPI communication, slave must reply whenever the master produces clock signal. But master can produces clock signal during slave (DSP) is in control ISR. In that case, slave can not reply and data is lost.

Hi Hakan,

For "when I enter the timer ISR, I re-enable global ISR and let PWM ISR to interrupt timer ISR", does that mean a nested interrupt implementation ?

processors.wiki.ti.com/.../Interrupt_Nesting_on_C28x

Hi Zy,

Yes. What I did was definitely interrupt nesting. Unfortunately, I was not aware of the link you sent until now. I wish to know it while I was coding :) It is a good source by the way.

Hakan

Thanks a lot for all the information :)