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ADC Sample rate vs. PWM frequency philosophy

Other Parts Discussed in Thread: TMS320F28335

I'm designing a three phase interleaved power factor corrected boost converter with a TMS320F28335.  My plan is to have three interleaved boost stages with their own individual current loops and one outer voltage loop to regulate the output voltage.

In previous projects I've always set the ADC up in cascaded sequencer mode.  I think the best way to set up the ADC for this project is to operate in dual sequencer mode, with SEQ1 handling the individual phase currents at the switching frequency (10KHz) and SEQ2 handling the slower changing analog inputs (output voltage, heatsink temp, etc) at a lower rate.

My concern is instability due to the lag between the A-D conversion and loading the PWM CMPx registers.  What is the best way to do this?  Is the optimum scheme (if you've got the time) to sample the individual phase currents at 3 or 4 times the switching frequency, then call the function that calculates the PWM CMPx values immediately after the ADC is complete.  It seems to me that this would reduce the lag in the feedback, improving stability.   If you sample at the switching frequency, since the PWMs are phase staggered, the CMPx register of the last staggered PWM will be loaded ((240degrees/360degrees) * 100uS) 66.6uS after the first PWM.  I would think that this would make this third phase less stable than the first phase.  Do you need to compensate it differently?

SEQ2 could be triggered at a lower rate, say 1 or 2 KHz to close the slow outer voltage loop and generate the other slow changing analog values.

Insight from an expert on the subject would be greatly appreciated.

  • Are you doing a 3-phase PFC for 3-phase AC input supply, or, it is an Interleaved PFC (3 interleaved phases ) with single phase AC input?

    If it is the latter then you have single input AC current to shape (improve power factor) and so you should sense the total current (of all three phases) and then implement single current control loop to shape that current. In this case you minimize the delay (ADC sampling to PWM duty update) by properly selecting the ADC SOC and PWM duty update. Pls see our 2-phase Interleaved PFC implementation (TMDSILPFCKIT) doc.

    Shamim
  • Shamim,

    Thanks for the response.   

    The application uses three interleaved phases for a single phase AC input.  You are correct, we could sum the three interleaved currents (we have provisions on the board to do so in hardware) and implement a single current loop.  This is an option, but not the preferred control scheme.  By not controlling each current individually, any deviation in ESR or inductance in the interleaving inductors (believe it or not even in dead time in IGBT switching) will result in mismatches between the three interleaved currents.  We have designed several interleaved topologies, and we've seen this mismatch.

    Like I said, one option is to group the inductors into matched sets and use the single current loop, but I was hoping to mitigate this problem with software.  Before we attempted this DSP solution, we used a control board with lots and lots of chips and discretes to perform the current balancing.

    Since the next design after completing the single phase PFC application, naturally is a three phase PFC application, I'll need to know how to control three current loops anyway.  So is the scheme that I mentioned that samples at a rate several times the PWM frequency valid?

    Specific questions:

    1.  The three interleaved IGBTs are controlled by ePWM1, 2, and 3 switch at 10KHz and the ADC is called by ePWM4 at 40KHz.  Assuming ePWM4 and the interleaved IGBTs are synchronous, the last statement in the ADC ISR will call the function to calculate the PWM CMP registers every 25uS.  Therefore, the longest lag between the ADC read and CMP register load will be 25uS, usually closer to 10 or 15uS.  This has to be better than reading analog inputs at 10KHz and potentially waiting close to 100uS before loading the CMP register.  Yes?  What is the optimum technique?  Please do not refer me to a kit.

    2.  When setting up the ADC for dual sequencer mode, do the conversions in SEQ2 have to be completed before going back to make the conversions in SEQ1?  Essentially, can I convert heatsink temp, DC bus voltage, etc. at 1KHz in SEQ2 while I'm converting current feedback for the fast control loop at 40KHz in SEQ1?

  • 2. There is only one ADC converter, so each sequence is serviced one-at-a-time. You will want to make sure that SEQ2 doesn't start right before SEQ1, otherwise your SEQ1 results will be slightly delayed.

    My guess is that you may want to set SEQ2 to operate off of ePWM - SOCB, using the same 40KHz ePWM, but set the SOC event divider higher (every 2nd or 3rd compare). You shouldn't need to skew SOCB to occur later because SEQ1 has priority if they are both triggered at the same time. This gives a sample rate on the lower priority channels of 20KHz or 13.33KHz. If this is too high from an ISR overhead perspective, then using the DMA to accumulate X samples, then trigger the ISR to reduce the ISR overhead by a factor of X (you can average the accumulated samples, or just use the latest one).