I'm designing a three phase interleaved power factor corrected boost converter with a TMS320F28335. My plan is to have three interleaved boost stages with their own individual current loops and one outer voltage loop to regulate the output voltage.
In previous projects I've always set the ADC up in cascaded sequencer mode. I think the best way to set up the ADC for this project is to operate in dual sequencer mode, with SEQ1 handling the individual phase currents at the switching frequency (10KHz) and SEQ2 handling the slower changing analog inputs (output voltage, heatsink temp, etc) at a lower rate.
My concern is instability due to the lag between the A-D conversion and loading the PWM CMPx registers. What is the best way to do this? Is the optimum scheme (if you've got the time) to sample the individual phase currents at 3 or 4 times the switching frequency, then call the function that calculates the PWM CMPx values immediately after the ADC is complete. It seems to me that this would reduce the lag in the feedback, improving stability. If you sample at the switching frequency, since the PWMs are phase staggered, the CMPx register of the last staggered PWM will be loaded ((240degrees/360degrees) * 100uS) 66.6uS after the first PWM. I would think that this would make this third phase less stable than the first phase. Do you need to compensate it differently?
SEQ2 could be triggered at a lower rate, say 1 or 2 KHz to close the slow outer voltage loop and generate the other slow changing analog values.
Insight from an expert on the subject would be greatly appreciated.