Other Parts Discussed in Thread: TMS320F28069
I am trying to perform Level 2 build in “BLDC Sensored” project in Control suite. The kit I’m using is DRV8312-28069M which has TMS320F28069 control card. I have a slight doubt in the BLDC_PWM macro that is used in this code. I have attached the code snippet below. Going by the code I find that when the output of mod6_cnt is 0, the EPWM1A is kept always high and EPWM1B is provided with PWM signal of 20kHz. The BLDC_3PWM macro explanation in DMC library shows that the upper leg of the first bridge must be provided with PWM and the lower leg of the second bridge to be HIGH (which I can see happening in the code according to the Action qualifier registers). But, the board schematic shows that EPWM1A is connected to the upper leg of the first bridge. Could someone explain if I have contrived something wrong here? This doubt comes about since I want to know how the Dutyfunc depends on the Duty cycle of the PWM signal provided.
#define BLDCPWM_MACRO(v) /* */\
/* Convert "Period" (Q15) modulation function to Q0 */\
Tmp = (int32)v.PeriodMax*(int32)v.MfuncPeriod; /* Q15 = Q0xQ15 */\
Period = (int16)(Tmp>>15); /* Q15 -> Q0 (Period) */\
/* */\
/* Check PwmActive setting */\
if (v.PwmActive==1) /* PWM active high */\
{ /* */\
GPR0_BLDC_PWM = 0x7FFF - v.DutyFunc; /* */\
CMPB_SMPL_POINT = 0x7FFF - (v.DutyFunc >> 1); /* Sample in center of PWM pulse using CMPB */\
} /* */\
/* */\
else if (v.PwmActive==0) /* PWM active low */\
{ /* */\
GPR0_BLDC_PWM = v.DutyFunc; /* */\
CMPB_SMPL_POINT = v.DutyFunc >> 1; /* Sample in center of PWM pulse using CMPB */\
} /* */\
/* */\
/* Convert "DutyFunc" or "GPR0_BLDC_PWM" (Q15) duty modulation function to Q0 */\
Tmp = (int32)Period*(int32)GPR0_BLDC_PWM; /* Q15 = Q0xQ15, Period=25us */\
Tmp2 = (int32)Period*(int32)CMPB_SMPL_POINT; /* Q15 = Q0xQ15 */\
EPwm1Regs.CMPB = (int16)(Tmp2>>15); /* Sample in center of PWM pulse using CMPB */\
/* */\
/* State s1: current flows to motor windings from phase A->B, de-energized phase = C */\
if (v.CmtnPointer==0) /* */\
{ /* */\
EPwm1Regs.AQCSFRC.bit.CSFB = 0; /* Continuous s/w Forcing feature disabled on output B of EPWM1 */\
EPwm1Regs.AQCTLB.bit.CAU = 2; /* Set high when CTR = CMPA on UP-count */\
EPwm1Regs.AQCTLB.bit.ZRO = 1; /* Set low when CTR = Zero */\
EPwm1Regs.CMPA.half.CMPA = (int16)(Tmp>>15); /* PWM signal on output B of EPWM1 (Q15 -> Q0) */\
EPwm1Regs.AQCSFRC.bit.CSFA = 2; /* Forcing a continuous High on output A of EPWM1 */\
/* */\
EPwm2Regs.AQCSFRC.bit.CSFA = 1; /* Forcing a continuous Low on output A of EPWM2 */\
EPwm2Regs.AQCSFRC.bit.CSFB = 2; /* Forcing a continuous High on output B of EPWM2(Lower leg of 2nd bridge) */\
/* */\
EPwm3Regs.AQCSFRC.bit.CSFA = 1; /* Forcing a continuous Low on output A of EPWM3 */\
EPwm3Regs.AQCSFRC.bit.CSFB = 1; /* Forcing a continuous Low on output B of EPWM3 */\
} /* */\
