I am confused when comparing some TMS320F2805 documentation regarding the minimum value of the sampling window (set by register ACQPS) while in the nonoverlap mode.
Table 6-33 on page 80 of the datasheet (Rev B) states that in nonoverlap mode the valid values for ACQPS are limited to: {15, 16, 28, 29, 41, 42, 54, 55}. OK, so this says that I have to provide for at least 16 (ACQPS + 1) ADC clock cycles for the sampling window in nonoverlap mode.
My confusion comes when I compare this to what is mentioned in the Technical Reference Manual (SPRUHE5B). It has this note in Figure 6-36 on page 473, "In this timing ADC sample window need not hold to 10 ADC clocks minimum". This seems strange, since figure 6-36 deals with the nonoverlap mode, so why would the note say the minimum sample window need not hold to a 10 ADC clock minimum, since the minimum window is 16 ADC clocks as was given in the datasheet (Table 6-33). Yes, I know the minimum in overlap mode is 10 ADC clocks, but that should be irrelevant since figure 6-36 covers only the nonoverlap mode.
Further, figure 6-36 indicates that the minimum sample window must be 166.67 ns (10 ADC clocks at 60 MHz, or 5 ADC clocks at 30 MHz). Either of these two values is less than is stated in Table 6-33 in the datasheet (although they do agree well with the note in figure 6-36 stating the minimum window need not hold to a 10 ADC clock minimum).
Table 6-4 (describing the ADCCTL2 register) on page 457 of the Technical Reference Manual seems to support the idea that the minimum window in nonoverlap mode can be less than the 16 ADC clocks specified in the datasheet when it says, "...when running /2 ADCCLK, scale the minimum sample duration accordingly to meet 116.6ns for better throughput." (I believe the "116.6ns" should read "166.67ns, TI does mention one revision of this typo in the revision list of Table A-1 on page 813.) So, if I have a 60 MHz CPU clock and set CLKDIV2EN to 1 in the ADCCTL2 register I should have a 30 MHz ADC clock and would thus only need an ACQPS value of 4 (gives 4+1 ADC clocks=166.67 ns for the sample window).
Lastly, the ACQPS field description in Table 6-18 on page 468 of the Technical Reference Manual states that the "Minimum value allowed is 6." So, the computed value of 4 for ACQPS above as required to meet the minimum 166.67 ns sample with a 30 MHz ADC clock is not a valid value. This is strange since it was the note in Table 6-4 the specifically says, "...when running /2 ADCCLK, scale the minimum sample duration accordingly to meet 116.6ns for better throughput." which would mean setting ACQPS to 4 (for a 60 MHz CPU clock) or to something even smaller for a lower CPU clock.
Perhaps it's just me, but I'm finding it hard to reconcile the seemingly disparate information mentioned above.
So, what is the minimum value ACQPS should be set to in nonoverlap mode?
Thank you for any assistance,
Mark
